Semiconductor package and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2018197831-A1
Application number	US-201715788189-A
Country	US
Kind code	A1
Filing date	Oct 19, 2017
Priority date	Jan 11, 2017
Publication date	Jul 12, 2018
Grant date	—

Abstract

A semiconductor package includes a substrate portion including a core layer having a device accommodating portion formed therein, and a buildup layer stacked on each of opposing sides of the core layer; an electronic device disposed in the device accommodating portion; and heat dissipating conductors disposed in the buildup layer to externally emit heat generated by the electronic device.

First claim

What is claimed is:

1 . A semiconductor package, comprising:
a substrate portion comprising a core layer having a device accommodating portion formed therein, and a buildup layer stacked on each of opposing sides of the core layer; an electronic device disposed in the device accommodating portion; and heat dissipating conductors disposed in the buildup layer to externally emit heat generated by the electronic device.

2 . The semiconductor package of claim 1 , wherein the electronic device has an active surface having a terminal formed therein and an inactive surface opposite to the active surface, and the heat dissipating conductor is connected to the inactive surface.

3 . The semiconductor package of claim 1 , further comprising:
an insulating protective layer disposed in the buildup layer, wherein the insulating protective layer comprises openings partially exposing the heat dissipating conductors.

4 . The semiconductor package of claim 2 , wherein one of the heat dissipating conductors is disposed opposite to the inactive surface of the electronic device.

5 . The semiconductor package of claim 3 , wherein the heat dissipating conductors comprise heat dissipating pads, a region externally exposed through the insulating protective layer, and
a total area of the heat dissipating pads is 35.5% or less of an area of the inactive surface of the electronic device.

6 . The semiconductor package of claim 5 , wherein the heat dissipating conductors are formed to allow a ratio D/P to be 67 or more, where D is a diameter of a heat dissipating pad of the heat dissipating pads and P is a separation distance between the heat dissipating pads.

7 . The semiconductor package of claim 1 , wherein the heat dissipating conductors are disposed in a lattice form.

8 . The semiconductor package of claim 1 , wherein a heat dissipating conductor of the heat dissipating conductors is disposed to pass through an insulating layer forming the buildup layer, one end of the heat dissipating conductor is connected to the electronic device, and the other end thereof is externally exposed through the buildup layer.

9 . The semiconductor package of claim 1 , wherein the electronic device is disposed in the device accommodating portion in a bare die state.

10 . A semiconductor package, comprising:
a first package comprising a core layer having an electronic device embedded therein, a buildup layer stacked on each of opposing sides of the core layer, and heat dissipating conductors disposed in the buildup layer to externally emit heat generated by the electronic device; and a second package mounted on the first package.

11 . The semiconductor package of claim 10 , further comprising:
a metal layer formed on surfaces of the first package and the second package to shield electromagnetic waves.

12 . A method of manufacturing a semiconductor package, comprising:
forming a device accommodating portion in the form of a through-hole in a core layer; disposing an electronic device in the device accommodating portion; and forming a buildup layer on each of opposing sides of the core layer, the buildup layer comprising an insulating layer and a distribution layer, wherein the forming the buildup layer comprises forming an heat dissipating conductor passing through the insulating layer to connect one end of the heat dissipating conductor to the electronic device and externally exposing the other end through the buildup layer.

13 . The semiconductor package of claim 12 , further comprising:
completing a first package by forming an insulating protective layer on the buildup layer, after the forming a buildup layer.

14 . The semiconductor package of claim 13 , further comprising:
mounting a second package, separately manufactured, on one surface of the first package.

Assignees

• Samsung Electro Mech

Inventors

• Kim Tae Hyun
• Kim Thomas A
• Han Kyu Bum

Classifications

• H10W42/273

  the arrangements being between laterally adjacent chips, e.g. walls between chips · CPC title

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title