Semiconductor package device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2018019221-A1
Application number	US-201715649545-A
Country	US
Kind code	A1
Filing date	Jul 13, 2017
Priority date	Jul 15, 2016
Publication date	Jan 18, 2018
Grant date	—

Abstract

A semiconductor package device includes a first die, an adhesive layer, and an encapsulant layer. The first die comprises a first electrode at a first surface of the first die and a second electrode at a second surface of the first die opposite to the first surface of the first die. The adhesive layer is disposed on the first surface of the first die. The encapsulant layer encapsulates the first die and the adhesive layer, wherein substantially an entire surface of the second electrode is exposed from the encapsulant layer.

First claim

What is claimed is:

1 . A semiconductor package device, comprising:
a first die having a first surface and a second surface opposite to the first surface, the first die comprising a first electrode disposed at the first surface of the first die and a second electrode disposed at the second surface of the first die; an adhesive layer disposed on the first surface of the first die; and an encapsulant layer encapsulating the first die and the adhesive layer, wherein substantially an entire surface of the second electrode is exposed from the encapsulant layer.

2 . The semiconductor package device of claim 1 , further comprising a first conductive layer disposed on the encapsulant layer, wherein the first conductive layer is in thermal and electrical communication with the second electrode and covers substantially the entire surface of the second electrode.

3 . The semiconductor package device of claim 2 , wherein a lateral surface of the encapsulant layer is substantially coplanar with a side surface of the first conductive layer.

4 . The semiconductor package device of claim 2 , further comprising a first conductive via disposed in the encapsulant layer electrically connected to the first conductive layer.

5 . The semiconductor package device of claim 4 , further comprising:
a second die disposed in the encapsulant layer; a second adhesive layer disposed on the second die and in the encapsulant layer; a second conductive via disposed in the second adhesive layer and electrically connected to the second die; a third conductive via disposed in the encapsulant layer and electrically connected to the first conductive layer; a patterned conductive layer disposed on the encapsulant layer and electrically connected to the first conductive via, the second conductive via and the third conductive via.

6 . The semiconductor package device of claim 5 , further comprising a first seed layer disposed between the third conductive via and the encapsulant layer.

7 . The semiconductor package device of claim 1 , further comprising a first conductive via disposed in the adhesive layer, wherein at least a portion of a surface of the first electrode is exposed from the adhesive layer and electrically connected to the first conductive via.

8 . The semiconductor package device of claim 7 , further comprising:
a first seed layer disposed between the first electrode and the first conductive via and between the first conductive via and the adhesive layer.

9 . The semiconductor package device of claim 1 , further comprising:
a first conductive via disposed in the first adhesive layer and electrically connected to the first die; a second die disposed in the encapsulant layer; a second adhesive layer disposed on the second die and in the encapsulant layer; a second conductive via disposed in the second adhesive layer and electrically connected to the second die; and a patterned conductive layer disposed on the encapsulant layer and electrically connected to the first conductive via and the second conductive via.

10 . The semiconductor package device of claim 9 , further comprising a first conductive layer disposed on the encapsulant layer and electrically connected to the second electrode.

11 . The semiconductor package device of claim 10 , further comprising a third conductive via disposed in the encapsulant layer and electrically connected to the first conductive layer.

12 . The semiconductor package device of claim 1 , further comprising a first conductive layer disposed on the second surface of the first die.

13 . The semiconductor package device of claim 1 , further comprising:
a first conductive via disposed in the first adhesive layer and electrically connected to the first die; and a patterned conductive layer disposed on the encapsulant layer and electrically connected to the first conductive via.

14 . A method of manufacturing a semiconductor package device, the method comprising:
providing a carrier having a first conductive layer disposed thereon; attaching a first side of a first die to the carrier through a first adhesive layer, the first die comprising a first electrode disposed at the first side and a second electrode disposed at a second side opposite to the first side; encapsulating the first die and the first adhesive layer with an encapsulant such that substantially an entire surface of the second electrode of the first die is exposed from the encapsulant; and removing the carrier.

15 . The method of claim 14 , further comprising removing a portion of the first conductive layer and a portion of the first adhesive layer to form an opening that exposes the first electrode.

16 . The method of claim 15 , further comprising filling the opening with a conductive material to form a first conductive via.

17 . The method of claim 14 , further comprising forming a second conductive layer on the encapsulant and electrically connecting the second conductive layer to the second electrode.

18 . The method of claim 17 , further comprising:
removing a portion of the first conductive layer and a portion of the first adhesive layer to form an opening that exposes the first electrode; and filling the opening with a conductive material to form a first conductive via, wherein the formation of the first conductive layer and the first conductive via is performed in a single operation.

19 . The method of claim 17 , further comprising:
removing a portion of the first conductive layer and a portion of the first adhesive layer to form an opening that exposes the first electrode; filling the first opening with a conductive material to form a first conductive via; and forming a second conductive via in the encapsulant.

20 . The method of claim 14 , further comprising:
forming a conductive stud adjacent to an area where the first die is to be placed on the carrier; encapsulating the conductive stud when encapsulating the first die and the first adhesive layer; and exposing the conductive stud.

Assignees

• Advanced Semiconductor Eng

Inventors

• Appelt Bernd Karl
• Essig Kay Stefan
• Chiu Chi-Tsung

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/9413

  on encapsulations · CPC title