Scanning Methods For Focus Control For Lithographic Processing Of Reconstituted Wafers

Patent metadata

Field	Value
Publication number	US-2018166348-A1
Application number	US-201715834614-A
Country	US
Kind code	A1
Filing date	Dec 7, 2017
Priority date	Dec 8, 2016
Publication date	Jun 14, 2018
Grant date	—

Abstract

A method of processing a reconstituted wafer that supports IC chips includes operably disposing the reconstituted wafer in a lithography tool that has a depth of focus and a focus plane and that defines exposure fields on the reconstituted wafer, wherein each exposure field includes at least one of the IC chips. The method also includes scanning the reconstituted wafer with a line scanner to measure a surface topography of the reconstituted wafer as defined by the IC chips. The method also includes, for each exposure field: i) adjusting a position and/or an orientation of the reconstituted wafer so that a photoresist layers of the IC chips within the given exposure field fall within the depth of focus; and ii) performing an exposure with the lithography tool to pattern the photoresist layers of the IC chips in the given exposure field.

First claim

What is claimed is:

1 . A method of processing a reconstituted wafer that supports integrated circuit (IC) chips each having an upper surface coated with a photoresist layer, comprising:
a) operably disposing the reconstituted wafer in a lithography tool that has a depth of focus and a focus plane and that defines exposure fields on the reconstituted wafer, wherein each exposure field includes at least one of the IC chips; b) performing at least one scan of the reconstituted wafer with a line scanner that comprises a plurality of height sensor elements arranged along a long direction to measure a surface topography of the reconstituted wafer, wherein the surface topography is defined by the plurality of IC chips; c) for a given exposure field:
i) adjusting at least one of a position and an orientation of the reconstituted wafer relative to the focus plane of a lithography tool so that the photoresist layers of the IC chips within the given exposure field fall within the depth of focus; and
ii) performing an exposure with the lithography tool to pattern the photoresist layers of the IC chips in the given exposure field; and
d) repeating act c) for each of the exposure fields.

2 . The method according to claim 1 , further comprising after act d):
e) processing the patterned photoresist layers of the IC chips to form respective conductive structures on the upper surfaces of the IC chips.

3 . The method according to claim 1 , wherein the height sensor elements each have a width W and a center-to-center spacing of S, wherein S>W, and further comprising:
in act b), performing a first scan of the upper surface of reconstituted wafer, then defining a shifted position of the line scanner by shifting the line scanner in the long direction relative to the reconstituted wafer by an amount equal to or greater than the width W of the height sensor elements, and then performing a second scan of the upper surface of reconstituted wafer with the line scanner in the shifted position.

4 . The method according to claim 1 , wherein the act b) of performing at least one scan of the reconstituted wafer includes moving the line scanner or the reconstituted wafer.

5 . The method according to claim 1 , wherein the act b) of performing at least one scan of the reconstituted wafer includes moving both the line scanner and the reconstituted wafer.

6 . The method according to claim 1 , further comprising processing the patterned photoresist layers to form respective redistribution layers that each includes conductive features.

7 . The method according to claim 1 , wherein the height sensor elements each have a width and a center-to-center spacing, and further comprising:
performing a first scan with a first center-to-center spacing; changing the center-to-center spacing to define a second center-to-center spacing; and performing a second scan with the second center-to-center spacing.

8 . The method according to claim 7 , wherein the height sensor elements are mechanically connected to a mechanical linkage, and wherein changing the center-to-center spacing includes activating the mechanical linkage.

9 . The method according to claim 1 , wherein the exposure fields have a field pitch in a cross-scan direction, the height sensor elements each have a width W and a center-to-center sensor spacing of S, wherein S>W, and wherein S is an integer fraction of the field pitch pF.

10 . The method according to claim 1 , wherein act b) includes making at least 3 and no greater than 1000 height measurements per exposure field.

Assignees

• Ultratech Inc

Inventors

• Bischoff Paul M
• True Emily M
• Ellis Raymond
• Crespin A J

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P76/2041

  Photolithographic processes · CPC title

• H10P72/0606

  Position monitoring, e.g. misposition detection or presence detection · CPC title

• H10P72/53

  using optical controlling means · CPC title

• H10W72/244

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title