Semiconductor die having edge with multiple gradients and method for forming the same

US2018166328A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2018166328-A1
Application numberUS-201715725558-A
CountryUS
Kind codeA1
Filing dateOct 5, 2017
Priority dateDec 14, 2016
Publication dateJun 14, 2018
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for sawing a semiconductor wafer is provided. The method includes sawing a semiconductor wafer to form a first opening. In addition, the semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape by a die attach film (DAF), and the first opening is formed in an upper portion of the substrate. The method further includes sawing through the substrate and the DAF of the semiconductor wafer from the first opening to form a middle opening under the first opening and a second opening under the middle opening, so that the semiconductor wafer is divided into two dies. In addition, a slope of a sidewall of the middle opening is different from slopes of sidewalls of the first opening and the second opening.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method for sawing a semiconductor wafer, comprising: sawing a semiconductor wafer to form a first opening, wherein the semiconductor wafer comprises a dicing tape and a substrate attached to the dicing tape by a die attach film (DAF), and the first opening is formed in an upper portion of the substrate; and sawing through the substrate and the DAF of the semiconductor wafer from the first opening to form a middle opening under the first opening and a second opening under the middle opening, so that the semiconductor wafer is divided into two dies, wherein a slope of a sidewall of the middle opening is different from slopes of sidewalls of the first opening and the second opening. 2 . The method as claimed in claim 1 , further comprising: removing the dicing tape from the DAF. 3 . The method as claimed in claim 1 , wherein the first opening is formed by sawing the upper portion of the substrate by a first dicing blade, and the second opening is formed by sawing a bottom portion of the substrate and the DAF by a second dicing blade. 4 . The method as claimed in claim 3 , wherein a top portion of the dicing tape is also sawed by the second dicing blade. 5 . The method as claimed in claim 3 , wherein a width of the second dicing blade is less than a width of the first dicing blade. 6 . The method as claimed in claim 1 , further comprising; forming a material layer over the substrate before the first opening is formed; and forming a recess in the material layer to expose the substrate by an energy source. 7 . The method as claimed in claim 6 , wherein a sealing ring structure is formed in the material layer. 8 . The method as claimed in claim 6 , wherein a top portion of the substrate is sawed by the energy source when the recess is formed. 9 . The method as claimed in claim 1 , wherein a height of the first opening is smaller than a height of the second opening. 10 . A method for sawing semiconductor wafer, comprising: forming a first opening in a semiconductor wafer, wherein the semiconductor wafer comprises: a dicing tape; a substrate attached to the dicing tape by a die attach film (DAF); and a material layer formed over the substrate, wherein the first opening is formed in an upper portion of the substrate; and forming middle opening under the first opening and a second opening under the middle opening to divided the semiconductor wafer into two dies, wherein a sidewall of the first opening and a sidewall of the middle opening have different slopes. 11 . The method as claimed in claim 10 , wherein a width of the first opening is greater than a width of the second opening, and a width of the middle opening reduces gradually from an end closer to the first opening to an end closer to the second opening. 12 . The method as claimed in claim 10 , wherein the first opening is formed by sawing the upper portion of the substrate by a first dicing blade, and the middle opening and the second opening are formed by sawing the bottom portion of the substrate and the DAF by a second dicing blade. 13 . The method as claimed in claim 12 , wherein a height of the first opening is smaller than a sum of a height of the second opening and a height of the middle opening. 14 . The method as claimed in claim 10 , wherein the second opening extends into the dicing tape. 15 . The method as claimed in claim 14 , further comprising: removing the dicing tape from the DAF. 16 . The method as claimed in claim 10 , further comprising: sawing the material layer and the substrate by an energy source to form a recess before the first opening is formed. 17 . A semiconductor die, comprising: a die attach film (DAF); a substrate having a first primary segment, a middle segment, and a second primary segment disposed on the DAF; and a material layer formed on a top surface of the substrate, wherein a slope of a sidewall of the middle segment is different from slopes of sidewalls of the first primary segment and the second primary segment, and a height of the first primary segment is smaller than a height of the second primary segment. 18 . The semiconductor die as claimed in claim 17 , wherein a seal ring structure is formed in the material layer. 19 . The semiconductor die as claimed in claim 17 , wherein a ratio of a height of the first primary segment to a height of the second primary segment is in a range from about ½ to about ⅓. 20 . The semiconductor die as claimed in claim 17 , wherein an angle between the sidewall of the first primary segment and a line vertical to a top surface of the substrate is in a range from about 0 degree to about 30 degrees.

Assignees

Inventors

Classifications

  • the wafer tape being a laminate of three or more layers, e.g. including additional layers beyond a base layer and an uppermost adhesive layer · CPC title

  • Wafer tapes, e.g. grinding or dicing support tapes · CPC title

  • Apparatus for placing on an insulating substrate, e.g. tape · CPC title

  • Apparatus for mechanical treatment or grinding or cutting · CPC title

  • Apparatus for manufacture or treatment · CPC title

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What does patent US2018166328A1 cover?
A method for sawing a semiconductor wafer is provided. The method includes sawing a semiconductor wafer to form a first opening. In addition, the semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape by a die attach film (DAF), and the first opening is formed in an upper portion of the substrate. The method further includes sawing through the substrate and the D…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P72/0428. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jun 14 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).