Atomic Layer Etch Process Using Plasma In Conjunction With A Rapid Thermal Activation Process

Patent metadata

Field	Value
Publication number	US-2018166296-A1
Application number	US-201715582896-A
Country	US
Kind code	A1
Filing date	May 1, 2017
Priority date	Dec 14, 2016
Publication date	Jun 14, 2018
Grant date	—

Abstract

A process for etching a film layer on a semiconductor wafer is disclosed. The process is particularly well suited to etching carbon containing layers, such as hardmask layers, photoresist layers, and other low dielectric films. In accordance with the present disclosure, a reactive species generated from a plasma is contacted with a surface of the film layer. Simultaneously, the substrate or semiconductor wafer is subjected to rapid thermal heating cycles that increase the temperature past the activation temperature of the reaction in a controlled manner.

First claim

What is claimed is:

1 ) A process for etching a layer on a semiconductor wafer comprising:
placing a semiconductor wafer in a processing chamber, the semiconductor wafer including a film layer; generating a plasma from an etchant gas, the plasma containing a reactive species; contacting the film layer with the reactive species; and exposing the semiconductor wafer to a rapid thermal cycle while being contacted with the reactive species, the rapid thermal cycle heating the film layer above an activation temperature sufficient to cause the reactive species to etch the film layer.

2 ) A process as defined in claim 1 , wherein the film layer contains carbon.

3 ) A process as defined in claim 1 , wherein the film layer comprises a dielectric layer having a low dielectric constant.

4 ) A process as defined in claim 1 , wherein the rapid thermal cycle is produced by a plurality of lamps.

5 ) A process as defined in claim 4 , wherein the film layer is exposed to multiple rapid thermal cycles, each rapid thermal cycle comprising a pulse of light energy.

6 ) A process as defined in claim 1 , wherein the film layer comprises a photoresist layer or a hardmask layer.

7 ) A process as defined in claim 1 , wherein the semiconductor wafer is exposed to multiple rapid thermal cycles for incrementally etching the film layer.

8 ) A process as defined in claim 1 , wherein the process comprises an atomic layer etch.

9 ) A process as defined in claim 1 , wherein each rapid thermal cycle has a cycle time of from 1 ms to about 10 s.

10 ) A process as defined in claim 1 , wherein the etchant gas comprises molecular oxygen, molecular nitrogen, argon, molecular hydrogen, water, hydrogen peroxide, carbon dioxide, sulfur dioxide, methane, carbonyl sulfide, fluoroform (trifluoromethane), tetrafluoromethane, or mixtures thereof.

11 ) A process as defined in claim 1 , wherein the film layer contains amorphous carbon.

12 ) A process as defined in claim 1 , wherein the plasma is generated in a plasma chamber and is fed through a filter structure prior to contacting the film layer.

13 ) A process as defined in claim 1 , wherein the semiconductor wafer is heated to a temperature of from about 100° C. to about 300° C.

14 ) A process as defined in claim 12 , wherein the filter structure includes openings that allow reactive species to pass but filter out at least 65% of charged species contained within the plasma, the reactive species comprising neutral particles.

15 ) A process as defined in claim 12 , wherein the filter structure includes openings that allow reactive species to pass but filter out at least 85% of charged species contained within the plasma, the reactive species comprising neutral particles.

16 ) A process as defined in claim 1 , wherein the activation temperature is greater than about 80° C.

17 ) A process as defined in claim 1 , wherein the film layer is etched at an etch rate, the etch rate being from about 100 Angstroms per minute to about 5000 Angstroms per minute.

18 ) A process as defined in claim 5 , wherein the rapid thermal cycles have different cycle times.

19 ) A process as defined in claim 5 , wherein the temperature of the semiconductor wafer is increased in a nonlinear manner.

20 ) A process as defined in claim 1 , wherein the reactive species are introduced into the chamber opposite a top surface of the semiconductor wafer and wherein the rapid thermal cycle is produced by a plurality of lamps located below the semiconductor wafer.

Assignees

• Mattson Tech Inc

Inventors

• Ma Shawming

Classifications

• H10P95/08

  Planarisation of organic insulating materials · CPC title

• H10P50/287 Primary

  by chemical means · CPC title

• H01J37/32422

  Arrangement for selecting ions or species in the plasma · CPC title

• H01J37/32357

  Generation remote from the workpiece, e.g. down-stream · CPC title

• H01J37/32724

  Temperature · CPC title