Nanowire field effect transistor (FET) and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9887264-B2
Application number	US-201615245851-A
Country	US
Kind code	B2
Filing date	Aug 24, 2016
Priority date	Dec 10, 2015
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

A semiconductor structure includes a plurality of semiconductor fins located on a semiconductor substrate, in which each of the semiconductor fins comprises a sequential stack of a buffered layer including a III-V semiconductor material and a channel layer including a III-V semiconductor material. The semiconductor structure further includes a gap filler material surrounding the semiconductor fins and including a plurality of trenches therein. The released portions of the channel layers of the semiconductor fins located in the trenches constitute nanowire channels of the semiconductor structure, and opposing end portions of the channel layers of the semiconductor fins located outside of the trenches constitute a source region and a drain region of the semiconductor structure, respectively. In addition, the semiconductor structure further includes a plurality of gates structures located within the trenches that surround the nanowire channels in a gate all around configuration.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, comprising:
forming a plurality of semiconductor fins on a top surface of a semiconductor substrate, wherein at least one of the plurality of semiconductor fins includes a sequential stack of a buffered layer, a sacrificial layer and a channel layer, wherein the buffered layer, the sacrificial layer and the channel layer each include a III-V semiconductor material, wherein each semiconductor fin of the plurality of semiconductor fins includes a patterned hard mask located thereon;
removing each of the patterned hard masks to physically expose sidewalls and a topmost surface of each channel layer;
forming a plurality of dummy gate structures straddling over a portion of the channel layer of the semiconductor fins at a location between a first end and a second end of the channel layer, wherein each dummy gate structure directly contacts the physically exposed sidewalls and a topmost surface of the channel layer;
depositing a gap filler material surrounding the dummy gate structures;
removing the dummy gate structures to form a plurality of trenches in the gap filler material; and
releasing a portion of the channel layer of the semiconductor fins located within the trenches by removing portions of the sacrificial layer located beneath the portion of the channel layer within the trenches to form nanowire channels of the semiconductor structure from the released portions of channel layer of the semiconductor fins.

2. The method of claim 1 , further comprising forming a plurality of replacement gate structures within the trenches and that surround the nanowire channels of the semiconductor structure in a gate all around configuration.

3. The method of claim 1 , wherein the semiconductor substrate includes silicon, wherein the buffered layer includes one of gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium phosphide (GaP).

4. The method of claim 3 , wherein the sacrificial layer includes of indium phosphide (InP), indium aluminum arsenide (InAlAs), aluminum arsenide (AlAs), or a bilayer of indium phosphide (InP)/indium aluminum arsenide (InAlAs).

5. The method of claim 3 , wherein the channel layer includes indium gallium arsenide (InGaAs).

6. The method of claim 1 , wherein the buffered layer, the sacrificial layer and the channel layer are each deposited using metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

7. The method of claim 1 , wherein the forming the plurality of semiconductor fins comprises:
sequentially depositing the buffered layer, the sacrificial layer and the channel layer utilizing metal organic chemical vapor deposition or molecular beam epitaxy;
forming a hard mask material on the channel layer; and
patterning the hard mask material, the channel layer, the sacrificial layer and the buffered layer.

8. The method of claim 7 , wherein said patterning includes an etch that stops within the buffered layer.

9. The method of claim 1 , further comprising forming a trench isolation oxide in gaps located between each semiconductor prior to forming the plurality of dummy gate structures.

10. The method of claim 1 , further comprising forming spacers on opposing sidewalls of each dummy gate structure prior to depositing the gap filler material.

11. The method of claim 1 , further comprising cutting the semiconductor fins and epitaxially growing a semiconductor material to merge the channel layer of each cut semiconductor fin, wherein the cutting and the epitaxially growing are performed after forming the dummy gate structures and prior to depositing the gap filler material.

12. A semiconductor structure, comprising:
a plurality of semiconductor fins located on a semiconductor substrate, wherein each of the semiconductor fins comprises a sequential stack of a buffered layer including a III-V semiconductor material and a channel layer including a III-V semiconductor material;
a gap filler material surrounding the semiconductor fins and including a plurality of trenches therein, wherein released portions of the channel layers of the semiconductor fins located in the trenches constitute nanowire channels of the semiconductor structure, and wherein opposing end portions of the channel layers of the semiconductor fins located outside of the trenches constitute a source region and a drain region of the semiconductor structure, respectively; and
a plurality of gates structures located within the trenches, that surround the nanowire channels in a gate all around configuration, and wherein the gap filler material directly contacts a sidewall surface of a patterned portion of the buffered layer and a topmost surface of a non-patterned portion of the buffered layer, and has a topmost surface that is coplanar with each of the gate structures.

13. The semiconductor structure of claim 12 , wherein the semiconductor substrate is a bulk semiconductor substrate including silicon.

14. The semiconductor structure of claim 12 , wherein the buffered layer includes one of gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium phoshide (GaP), and wherein the channel layer includes indium gallium arsenide (InGaAs).

15. The semiconductor structure of claim 12 , further comprising:
a recessed shallow trench isolation (STI) oxide surrounding a lower portion of the semiconductor fins located beneath a lowermost surface of the channel layer of the semiconductor fins.

16. The semiconductor structure of claim 12 , further comprising:
spacers located on opposing sidewalls of the gate structures.

17. The semiconductor structure of claim 12 , wherein the gate structures each include a gate dielectric layer and a gate electrode stacked on the gate dielectric layer, and wherein the gate electrode of the gate structures each comprise at least one metal or poly-silicon.

Assignees

• IBM

Inventors

• Chu Jack O
• Cheng Szu Lin
• Lauer Isaac
• Shiu Kuen Ting
• Yau Jeng Bang

Classifications

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3421

  Arsenides · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title