Method for manufacturing an electronic device and electronic device

Patent metadata

Field	Value
Publication number	US-2018096984-A1
Application number	US-201715719599-A
Country	US
Kind code	A1
Filing date	Sep 29, 2017
Priority date	Oct 4, 2016
Publication date	Apr 5, 2018
Grant date	—

Abstract

A method for manufacturing an electronic device includes: providing a semiconductor carrier including first and second vertically integrated electronic structures laterally spaced apart from each other, an electrical connection layer disposed over a first side of the semiconductor carrier and electrically connecting the first and second vertically integrated electronic structures with each other; mounting the semiconductor carrier on a support carrier with the first side of the semiconductor carrier facing the support carrier; thinning the semiconductor carrier from a second side opposite the first side; and removing material of the semiconductor carrier in a separation region between the first and second vertically integrated electronic structures to separate a first semiconductor region of the first vertically integrated electronic structure from a second semiconductor region of the second vertically integrated electronic structure with the first and second vertically integrated electronic structures remaining electrically connected with each other via the electrical connection layer.

First claim

What is claimed is:

1 . A method for manufacturing an electronic device, the method comprising:
providing a semiconductor carrier, the semiconductor carrier comprising a first vertically integrated electronic structure and a second vertically integrated electronic structure laterally spaced apart from each other, an electrical connection layer disposed over a first side of the semiconductor carrier and electrically connecting the first vertically integrated electronic structure and the second vertically integrated electronic structure with each other; mounting the semiconductor carrier on a support carrier with the first side of the semiconductor carrier facing the support carrier; thinning the semiconductor carrier from a second side of the semiconductor carrier opposite the first side of the semiconductor carrier; and removing material of the semiconductor carrier in a separation region between the first vertically integrated electronic structure and the second vertically integrated electronic structure to separate a first semiconductor region of the first vertically integrated electronic structure from a second semiconductor region of the second vertically integrated electronic structure with the first vertically integrated electronic structure and the second vertically integrated electronic structure remaining electrically connected with each other via the electrical connection layer.

2 . The method of claim 1 ,
wherein the electrical connection layer comprises:
at least one first via embedded in dielectric material and electrically contacting at least one first contact region of the first vertically integrated electronic structure;
at least one second via embedded in dielectric material and electrically contacting at least one second contact region of the second vertically integrated electronic structure; and
one or more metal lines embedded in dielectric material, the one or more metal lines laterally electrically connecting the at least one first via and the at least one second via with each other.

3 . The method of claim 1 ,
wherein the electrical connection layer is at least partially exposed by removing the material of the semiconductor carrier in the separation region.

4 . The method of claim 1 ,
wherein mounting the semiconductor carrier on the support carrier comprises adhering the electrical connection layer to the support carrier via an adhesive layer or via bonding.

5 . The method of claim 1 ,
wherein thinning the semiconductor carrier comprises reducing a thickness of the semiconductor carrier to less than 15 μm.

6 . The method of claim 1 , further comprising:
after thinning the semiconductor carrier, forming a first contact structure disposed on the second side of the semiconductor carrier to electrically contact the first vertically integrated electronic structure and forming a second contact structure disposed on the second side of the semiconductor carrier to electrically contact the second vertically integrated electronic structure.

7 . The method of claim 6 ,
wherein the first contact structure has substantially the same lateral extension as the first semiconductor region of the first vertically integrated electronic structure and the second contact structure has substantially the same lateral extension as the second semiconductor region of the second vertically integrated electronic structure.

8 . The method of claim 1 , further comprising:
after removing the material of the semiconductor carrier in the separation region, forming a first passivation structure laterally surrounding the first semiconductor region of the first vertically integrated electronic structure and forming a second passivation structure laterally surrounding the second semiconductor region of the second vertically integrated electronic structure.

9 . The method of claim 1 , further comprising:
forming at least one trench structure in to support carrier, the at least one trench structure laterally surrounding at least one support carrier region, wherein the semiconductor carrier is mounted to the support carrier so that the first vertically integrated electronic structure and the second vertically integrated electronic structure are aligned with the support carrier region.

10 . The method of claim 1 ,
wherein the first vertically integrated electronic structure is a first vertical electrostatic discharge protection structure and wherein the second vertically integrated electronic structure is a second vertical electrostatic discharge protection structure.

11 . A method for manufacturing an electronic device, the method comprising:
providing a semiconductor carrier, the semiconductor carrier comprising a first vertically integrated electronic structure and a second vertically integrated electronic structure laterally spaced apart from each other, an electrical connection layer disposed over a first side of the semiconductor carrier electrically connecting the first vertically integrated electronic structure and the second vertically integrated electronic structure with each other; mounting the semiconductor carrier on a support carrier, wherein the electrical connection layer faces the support carrier; thinning the semiconductor carrier from a second side of the semiconductor carrier opposite the first side of the semiconductor carrier; subsequently, forming a patterned seed layer at the second side of the semiconductor carrier, wherein exposed portions of the semiconductor carrier between the first vertically integrated electronic structure and the second vertically integrated electronic structure are free of the patterned seed layer; removing material of the semiconductor carrier in the exposed portions; forming a sidewall passivation laterally surrounding the first vertically integrated electronic structure and the second vertically integrated electronic structure respectively; forming a first contact pad on the patterned seed layer via an electroless plating process, the first contact pad electrically contacting the first vertically integrated electronic structure; and forming a second contact pad on the patterned seed layer via an electroless plating process, the second contact pad electrically contacting the second vertically integrated electronic structure.

12 . An electrostatic discharge protection device comprising:
a first vertically integrated electrostatic discharge protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated electrostatic discharge protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated electrostatic discharge protection structure and the second vertically integrated electrostatic discharge protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layer, wherein the electrical connection layer is mounted on a support carrier via at least one adhesive layer.

13 . The electrostatic discharge protection device of claim 12 ,
wherein the electrical connection layer is partially exposed i

Assignees

• Infineon Technologies Ag

Inventors

• Schmenn Andre
• Pompl Stefan
• Sojka Damian
• Umminger Katharina

Classifications

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/01935

  by plating, e.g. electroless plating or electroplating · CPC title

• H10W72/0198

  batch processes · CPC title