Incremental parasitic extraction for coupled timing and power optimization

Patent metadata

Field	Value
Publication number	US-2018068052-A1
Application number	US-201715811826-A
Country	US
Kind code	A1
Filing date	Nov 14, 2017
Priority date	Dec 18, 2015
Publication date	Mar 8, 2018
Grant date	—

Abstract

An incremental parasitic extraction system includes a noise analysis module configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net. The incremental parasitic extraction system further includes an optimizer module and an extraction module. The optimizer module performs a first optimization activity on the at least one first net based on results of the first noise analysis. The optimizer module further generates a first invalidation list based on the first optimization activity, and a second invalidation list based on a type of the first optimization action so as to add the second invalidation list to the first invalidation list. The extraction module processes the first and second invalidation lists and performs an extraction and noise analysis process on the first and second invalidation lists so as to determine at least one new RC network and associated noise analysis results.

First claim

What is claimed is:

1 . A method of optimizing a semiconductor device according to a non-coupling scenario, the method comprising:
constructing an initial logic circuit including a plurality of initial design components; performing at least one first optimization action on the initial logic circuit, the at least one optimization action resulting in an updated performance requirement of at least one affected design component among the plurality of initial design components; generating an invalidation list that indicates the at least one affected design component; replacing the at least one affected design component with an updated design component capable of operating according to the updated performance requirement to construct an updated logic circuit; and performing at least one second optimization action on the updated logic circuit, the at least one second optimization action generating performance results of the updated design component along with the remaining initial design components without requiring coupling, wherein the at least one new RC network is implemented in a semiconductor device design and the semiconductor device including the at least one new RC network is fabricated based on the semiconductor device design.

2 . The method of claim 1 , wherein the at least one second optimization action is performed on each updated design component and each remaining initial design components before generating the performance results.

3 . The method of claim 2 , wherein the invalidation list includes initial design components physically connected to the replaced component, while excluding initial design components that are not physically connected to the replaced component.

4 . The method of claim 3 , wherein generating the invalidation list includes identifying parasitic noise of at least one aggressor net.

5 . The method of claim 4 , further comprising optimizing the semiconductor device based on extracted information corresponding to at least one new RC network and associated noise analysis results.

6 . The method of claim 5 , wherein the at least one new RC network includes at least one first net located adjacent the semiconductor device and at least one new aggressor net excluded from the first optimization activity.

7 . The method of claim 6 , wherein the first optimization activity includes at least one of layer promotion, layer demotion, buffer insertion, gate location change, gate type change, and logic equivalent port swap.

8 . The method of claim 7 , wherein the second optimization activity includes requesting timing optimization on the at least one first net.

9 . A non-coupling incremental parasitic extraction system comprising:
an initial logic circuit including a plurality of initial design components; an optimizer module including an electronic hardware controller configured to:
perform at least one first optimization action on the initial logic circuit, the at least one optimization action resulting in an updated performance requirement of at least one affected design component among the plurality of initial design components;
generate an invalidation list that indicates the at least one affected design component;
replace the at least one affected design component with an updated design component capable of operating according to the updated performance requirement to construct an updated logic circuit; and
perform at least one second optimization action on the updated logic circuit, the at least one second optimization action generating performance results of the updated design component along with the remaining initial design components without requiring coupling,
wherein the at least one new RC network is implemented in a semiconductor device design and the semiconductor device including the at least one new RC network is fabricated based on the semiconductor device design.

10 . The non-coupling incremental parasitic extraction system of claim 9 , wherein the at least one second optimization action is performed on each updated design component and each remaining initial design components before generating the performance results.

11 . The non-coupling incremental parasitic extraction system of claim 10 , wherein the invalidation list includes initial design components physically connected to the replaced component, while excluding initial design components that are not physically connected to the replaced component.

12 . The non-coupling incremental parasitic extraction system of claim 11 , wherein generating the invalidation list includes identifying parasitic noise of at least one aggressor net.

13 . The non-coupling incremental parasitic extraction system of claim 12 , further comprising optimizing the semiconductor device based on extracted information corresponding to at least one new RC network and associated noise analysis results.

14 . The non-coupling incremental parasitic extraction system of claim 13 , wherein the at least one new RC network includes at least one first net located adjacent the semiconductor device and at least one new aggressor net excluded from the first optimization activity.

15 . The non-coupling incremental parasitic extraction system of claim 14 , wherein the first optimization activity includes at least one of layer promotion, layer demotion, buffer insertion, gate location change, gate type change, and logic equivalent port swap.

16 . A computer program product to of optimize a semiconductor device according to a non-coupling scenario, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by an electronic computer processor to control the electronic device to perform operations comprising:
performing at least one first optimization action on an initial logic circuit including a plurality of initial design components, the at least one optimization action resulting in an updated performance requirement of at least one affected design component among the plurality of initial design components; generating an invalidation list that indicates the at least one affected design component; replacing the at least one affected design component with an updated design component capable of operating according to the updated performance requirement to construct an updated logic circuit; and performing at least one second optimization action on the updated logic circuit, the at least one second optimization action generating performance results of the updated design component along with the remaining initial design components without requiring coupling, wherein the at least one new RC network is implemented in a semiconductor device design and the semiconductor device including the at least one new RC network is fabricated based on the semiconductor device design.

17 . The computer program product of claim 16 , wherein the at least one second optimization action is performed on each updated design component and each remaining initial design components before generating the performance results.

18 . The computer program product of claim 17 , wherein the invalidation list includes initial design components physically connected to the replaced component, while excluding initial design components that are not physically connected to the replaced component.

19 . The computer program product of claim 18 , wherein generating the invalidation list includes identifying parasitic noise of at least one aggressor net.

20 . The computer

Assignees

• IBM

Inventors

• Kalafala Kerim
• Ko Tsz-Mei
• Ledalla Ravichander
• Lee Alice H
• Matheny Adam P
• Neves Jose L
• Schaeffer Gregory M

Classifications

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F2119/10

  Noise analysis or noise optimisation · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title