Building a hash table
US-9779123-B2 · Oct 3, 2017 · US
US2018060072A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2018060072-A1 |
| Application number | US-201615244570-A |
| Country | US |
| Kind code | A1 |
| Filing date | Aug 23, 2016 |
| Priority date | Aug 23, 2016 |
| Publication date | Mar 1, 2018 |
| Grant date | — |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
Systems and methods are provided for executing an instruction. The method may include loading a first vector into a first location, the first vector including a plurality of first data elements and loading a second vector into a second location, the second vector including a plurality of second data elements. The method may further include comparing the plurality of first data elements of the first vector to the plurality of data elements of the second vector and performing one or more operations on the plurality of first and second data elements based on at least one vector cross-compare instruction. The one or more operations include counting a number of data elements of the plurality of first and second data elements that satisfy at least one condition, counting a number of times specified values occur in the plurality of first and second data elements, and generating sequence counts for duplicated values.
Opening claim text (preview).
What is claimed is: 1 . A computer-implemented method for executing a Single Instruction, Multiple Data (SIMD) instruction on a processor, the method comprising: loading a first vector into a first location, the first vector including a plurality of first data elements; loading a second vector into a second location, the second vector including a plurality of second data elements; comparing the plurality of first data elements of the first vector to the plurality of second data elements of the second vector; and performing one or more operations on the plurality of first and second data elements by applying vector cross-compare instructions processed by partitioning the vector cross-compare instructions into comparison, selection, and reduction steps. 2 . The method of claim 1 , further comprising counting a number of data elements of the plurality of first and second data elements that satisfy at least one condition. 3 . The method of claim 1 , further comprising counting a number of times specified values occur in the plurality of first and second data elements. 4 . The method of claim 1 , further comprising generating sequence counts for duplicated values identified in the plurality of first and second data elements. 5 . The method of claim 1 , wherein one of the vector cross-compare instructions is a vector cross-compare and count instruction. 6 . The method of claim 1 , wherein one of the vector cross-compare instructions is a vector cross-compare and sequence instruction. 7 . The method of claim 1 , wherein one of the vector cross-compare instructions is a vector cross-compare equal instruction. 8 . The method of claim 1 , further comprising determining whether each fullword of the second vector is equal to at least one fullword of the first vector. 9 . The method of claim 1 , further comprising counting a number of fullwords in the first vector equal to each fullword in the second vector. 10 . The method of claim 1 , further comprising counting a rank of a word for each fullword in the second vector. 11 . A computer system for executing a Single Instruction, Multiple Data (SIMD) machine instruction in a central processing unit, the computer system comprising: a memory; and a processor in communications with the memory, wherein the computer system is configured to perform the steps of: loading a first vector into a first location, the first vector including a plurality of first data elements; loading a second vector into a second location, the second vector including a plurality of second data elements; comparing the plurality of first data elements of the first vector to the plurality of second data elements of the second vector; and performing one or more operations on the plurality of first and second data elements by applying vector cross-compare instructions processed by partitioning the vector cross-compare instructions into comparison, selection, and reduction steps. 12 . The computer system of claim 11 , wherein the one or more operations include counting a number of data elements of the plurality of first and second data elements that satisfy at least one condition. 13 . The computer system of claim 11 , wherein the one or more operations include counting a number of times specified values occur in the plurality of first and second data elements. 14 . The computer system of claim 11 , wherein the one or more operations include generating sequence counts for duplicated values identified in the plurality of first and second data elements. 15 . The computer system of claim 11 , wherein one of the vector cross-compare instructions is a vector cross-compare and count instruction. 16 . The computer system of claim 11 , wherein one of the vector cross-compare instructions is a vector cross-compare and sequence instruction. 17 . The computer system of claim 11 , wherein one of the vector cross-compare instructions is a vector cross-compare equal instruction. 18 . A non-transitory computer readable storage medium comprising a computer readable program for executing a Single Instruction, Multiple Data (SIMD) instruction on a processor, wherein the computer readable program when executed on a computer causes the computer to perform the steps of: loading a first vector into a first location, the first vector including a plurality of first data elements; loading a second vector into a second location, the second vector including a plurality of second data elements; comparing the plurality of first data elements of the first vector to the plurality of data elements of the second vector; and performing one or more operations on the plurality of first and second data elements by applying vector cross-compare instructions processed by partitioning the vector cross-compare instructions into comparison, selection, and reduction steps. 19 . The non-transitory computer readable storage medium of claim 18 , wherein the one or more operations include: counting a number of data elements of the plurality of first and second data elements that satisfy at least one condition; counting a number of times specified values occur in the plurality of first and second data elements; and generating sequence counts for duplicated values identified in the plurality of first and second data elements. 20 . The non-transitory computer readable storage medium of claim 19 , wherein the vector cross-compare instructions are selected from the group consisting of a vector cross-compare and count instruction, a vector cross-compare and sequence instruction, and a vector cross-compare equal instruction.
Compare instructions, e.g. Greater-Than, Equal-To, MINMAX · CPC title
controlled by a single instruction for multiple data lanes [SIMD] · CPC title
Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.