Hardware accelerator with locally stored macros
US-11119766-B2 · Sep 14, 2021 · US
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Derby Jeffrey H patents
Derby Jeffrey H is listed as an inventor on 24 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Derby Jeffrey H |
| Total patents | 24 |
| First publication | Mar 24, 2015 |
| Latest publication | Sep 14, 2021 |
Notable patents
Publications ranked by popularity score, then publication date.
Vector cross-compare count and sequence instructions
US-11061675-B2 · Jul 13, 2021 · US
Hardware accelerator with locally stored macros
US-2020183686-A1 · Jun 11, 2020 · US
Vector cross-compare count and sequence instructions
US-2020057637-A1 · Feb 20, 2020 · US
Vector cross-compare count and sequence instructions
US-10564964-B2 · Feb 18, 2020 · US
In-memory/register vector radix sort
US-10248419-B2 · Apr 2, 2019 · US
Sort-merge-join on a large architected register file
US-10042876-B2 · Aug 7, 2018 · US
Vector cross-compare count and sequence instructions
US-2018060072-A1 · Mar 1, 2018 · US
High-performance hash joins using memory with extensive internal parallelism
US-9817612-B2 · Nov 14, 2017 · US
High-performance hash joins using memory with extensive internal parallelism
US-9811287-B2 · Nov 7, 2017 · US
Recent patents
Latest publications not already listed above.
In-Memory/Register Vector Radix Sort
US-2017262211-A1 · Sep 14, 2017 · US
Merging and sorting arrays on an SIMD processor
US-9740659-B2 · Aug 22, 2017 · US
Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines
US-9710310-B2 · Jul 18, 2017 · US
Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines
US-9606838-B2 · Mar 28, 2017 · US
Correlating pseudonoise sequences in an SIMD processor
US-9584178-B2 · Feb 28, 2017 · US
High-performance hash joins using memory with extensive internal parallelism
US-2016147451-A1 · May 26, 2016 · US
High-performance hash joins using memory with extensive internal parallelism
US-2016147450-A1 · May 26, 2016 · US
Sort-merge-join on a large architected register file
US-2016078031-A1 · Mar 17, 2016 · US
Correlating pseudonoise sequences in an simd processor
US-2016020821-A1 · Jan 21, 2016 · US
Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines
US-2015355948-A1 · Dec 10, 2015 · US
Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines
US-2015355949-A1 · Dec 10, 2015 · US
Merging and Sorting Arrays on an SIMD Processor
US-2015269119-A1 · Sep 24, 2015 · US
Techniques for improving the efficiency of mixed radix fast fourier transform
US-9047230-B2 · Jun 2, 2015 · US
Techniques for improving the efficiency of mixed radix fast fourier transform
US-8990281-B2 · Mar 24, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 24 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/30036 | 14 |
| G06F9/30021 | 6 |
| G06F16/2456 | 6 |
| G06F3/0673 | 5 |
| G06F3/0611 | 4 |