Semiconductor device

Patent metadata

Field	Value
Publication number	US-2018019331-A1
Application number	US-201615544898-A
Country	US
Kind code	A1
Filing date	Feb 22, 2016
Priority date	Feb 25, 2015
Publication date	Jan 18, 2018
Grant date	—

Abstract

A semiconductor device includes: a semiconductor substrate having a drift layer; a base layer and a carrier storage layer over the drift layer; a collector layer on the drift layer opposite to the base layer; multiple trenches penetrating the base layer and the carrier storage layer and reaching the drift layer; a gate electrode on an insulation film in each trench; and an emitter region in a surface portion of the base layer contacting each trench. A thickness of at least a portion of a part of the gate insulation film on a sidewall of each trench on a collector layer side from a peak position, at which the impurity concentration of the carrier storage layer is highest, is thicker than a thickness of another part of the gate insulation film on the sidewall of an opening portion side of the trench from the peak position.

First claim

1 . A semiconductor device comprising:
a semiconductor substrate having a drift layer with a first conductive type; a base layer having a second conductive type and disposed on the drift layer; a carrier storage layer having the first conductive type with an impurity concentration higher than the drift layer, and arranged over the drift layer; a collector layer having the second conductive type and arranged on the drift layer opposite to the base layer; a plurality of trenches penetrating the base layer and the carrier storage layer, reaching the drift layer, and arranged along one direction of a planar direction of the semiconductor substrate; a gate insulation film arranged on a sidewall of each trench; a gate electrode arranged on the gate insulation film; and an emitter region having the first conductive type, arranged in a surface portion of the base layer, and contacting each trench, wherein: a thickness of at least a portion of a part of the gate insulation film arranged on a sidewall of each trench disposed on a collector layer side from a peak position, at which the impurity concentration of the carrier storage layer is highest, is thicker than a thickness of another part of the gate insulation film arranged on the sidewall of each trench disposed on an opening portion side of the trench from the peak position.

2 . The semiconductor device according to claim 1 , wherein:
the carrier storage layer has the peak position at a middle position of the carrier storage layer in a stacking direction of the drift layer and the base layer; and the thickness of the part of the gate insulation film arranged on the sidewall of each trench contacting the carrier storage layer disposed on the collector layer side from the peak position is thicker than the thickness of the another part of the gate insulation film arranged on the sidewall of each trench disposed on the opening portion side of the trench from the peak position.

3 . The semiconductor device according to claim 1 , wherein:
each trench includes a first trench providing an opening portion and arranged to the peak position and a second trench connecting to the first trench, reaching the drift layer, and having a distance between facing sidewalls longer than a distance between facing sidewalls of the first trench; the part of the gate insulation film arranged on the sidewall of the second trench is thicker than the another part of the gate insulation film arranged on the sidewall of the first trench; and a distance between adjacent second trenches is shorter than a distance between adjacent first trenches.

4 . The semiconductor device according to claim 1 , wherein:
each trench has a constant distance between facing sidewalls; the gate electrode includes a first gate electrode arranged from the opening portion side of the trench to the peak position and a second gate electrode connecting to the first gate electrode at the peak position and arranged on a bottom side of the trench; and the first gate electrode has a width larger than a width of the second gate electrode.

5 . The semiconductor device according to claim 1 , wherein:
the thickness of further another part of the gate insulation film arranged on a bottom of each trench is thicker than the thickness of the another part of the gate insulation film arranged on the sidewall of each trench disposed on the opening portion side of the trench from the peak position.

Assignees

• Denso Corp

Inventors

• Sumitomo Masakiyo
• Ogino Masahiro
• Kato Yukihiro

Classifications

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H01L23/485

  Electricity · mapped topic

• H01L29/78

  Electricity · mapped topic

• H01L29/7394 Primary

  Electricity · mapped topic

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title