Two-dimensional structure to form an embedded three-dimensional structure

US2017372831A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2017372831-A1
Application numberUS-201615192802-A
CountryUS
Kind codeA1
Filing dateJun 24, 2016
Priority dateJun 24, 2016
Publication dateDec 28, 2017
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Disclosed is an apparatus including a plurality of vias each having a defined shape, wherein each of the plurality of vias includes a first two-dimensional conductive layer plated on a first side of a substrate, the first two-dimensional conductive layer having the defined shape, a second two-dimensional conductive layer plated on a second side of the substrate, the second two-dimensional conductive layer having the defined shape, and a via conductively coupling the first two-dimensional conductive layer to the second two-dimensional conductive layer. The apparatus further includes a plurality of interconnects configured to conductively couple the plurality of vias, wherein the first two-dimensional conductive layer and the second two-dimensional conductive layer of each of the plurality of vias are perpendicular to the plurality of interconnects.

First claim

Opening claim text (preview).

What is claimed is: 1 . An apparatus, comprising: a plurality of vias each having a defined shape, wherein each of the plurality of vias comprises: a first two-dimensional conductive layer plated on a first side of a substrate, the first two-dimensional conductive layer having the defined shape, a second two-dimensional conductive layer plated on a second side of the substrate, the second two-dimensional conductive layer having the defined shape, and a via conductively coupling the first two-dimensional conductive layer to the second two-dimensional conductive layer; and a plurality of interconnects configured to conductively couple the plurality of vias, wherein the first two-dimensional conductive layer and the second two-dimensional conductive layer of each of the plurality of vias are perpendicular to the plurality of interconnects. 2 . The apparatus of claim 1 , wherein the apparatus comprises an inductor device. 3 . The apparatus of claim 2 , wherein the defined shape is a curved shape. 4 . The apparatus of claim 3 , further comprising a magnetic core of the inductor device within an aperture defined by the curved shape of the plurality of vias. 5 . The apparatus of claim 3 , wherein a length of the plurality of interconnects is less than a length of a second plurality of interconnects conductively coupling a second plurality of vias of a second inductor device, wherein the second plurality of vias do not have the curved shape. 6 . The apparatus of claim 2 , wherein the defined shape is an “I” shape. 7 . The apparatus of claim 6 , wherein a quality factor of the inductor device is greater than a second quality factor of a second inductor device, wherein a second plurality of vias of the second inductor device are drilled or cut vias. 8 . The apparatus of claim 1 , wherein the defined shape is a “C” shape. 9 . The apparatus of claim 1 , wherein the defined shape is a semicircle shape. 10 . The apparatus of claim 1 , wherein the apparatus comprises an embedded three-dimensional (3D) coil. 11 . A method for forming an embedded three-dimensional (3D) coil, comprising: forming a plurality of vias on a substrate, wherein forming each of the plurality of vias comprises: plating a first two-dimensional conductive layer on a first side of the substrate, the first two-dimensional conductive layer having a defined shape, plating a second two-dimensional conductive layer on a second side of the substrate, the second two-dimensional conductive layer having the defined shape, and forming a via through the substrate to conductively couple the first two-dimensional conductive layer to the second two-dimensional conductive layer; and forming a plurality of interconnects to conductively couple the plurality of vias, wherein the first two-dimensional conductive layer and the second two-dimensional conductive layer of each of the plurality of vias are perpendicular to the plurality of interconnects. 12 . The method of claim 11 , further comprising: dicing the substrate into a plurality of slivers, each of the plurality of slivers including at least one pair of vias of the plurality of vias; and attaching the plurality of slivers to a molding compound to form the embedded 3D coil, wherein the subset of the plurality of slivers form a row of pairs of vias of the plurality of vias. 13 . The method of claim 12 , wherein the plurality of interconnects conductively couples the pairs of vias of the plurality of vias. 14 . The method of claim 11 , further comprising forming a magnetic core of the embedded 3D coil within an aperture defined by the pairs of vias of the plurality of vias. 15 . The method of claim 11 , wherein the embedded 3D coil comprises an inductor device. 16 . The method of claim 15 , wherein the defined shape is a curved shape. 17 . The method of claim 16 , wherein a length of the plurality of interconnects is less than a length of a second plurality of interconnects conductively coupling a second plurality of vias of a second inductor device, wherein the second plurality of vias do not have the curved shape. 18 . The method of claim 15 , wherein the defined shape is an “I” shape. 19 . The method of claim 18 , wherein a quality factor of the inductor device is greater than a second quality factor of a second inductor device, wherein a second plurality of vias of the second inductor device are drilled or cut vias. 20 . The method of claim 11 , wherein the defined shape is a “C” shape. 21 . The method of claim 11 , wherein the defined shape is a semicircle shape. 22 . An apparatus, comprising: a plurality of vias each having a defined shape, wherein each of the plurality of vias comprises: a first two-dimensional conductive means plated on a first side of a substrate, the first two-dimensional conductive means having the defined shape, a second two-dimensional conductive means plated on a second side of the substrate, the second two-dimensional conductive means having the defined shape, and means for conductively coupling the first two-dimensional conductive means to the second two-dimensional conductive means; and a plurality of interconnects configured to conductively couple the plurality of vias, wherein the first two-dimensional conductive means and the second two-dimensional conductive means of each of the plurality of vias are perpendicular to the plurality of interconnects. 23 . The apparatus of claim 22 , wherein the apparatus comprises an inductor device. 24 . The apparatus of claim 23 , wherein the defined shape is a curved shape. 25 . The apparatus of claim 24 , further comprising a magnetic core of the inductor device within an aperture defined by the curved shape of the plurality of vias. 26 . The apparatus of claim 23 , wherein the defined shape is an “I” shape. 27 . The apparatus of claim 26 , wherein a quality factor of the inductor device is greater than a second quality factor of a second inductor device, wherein a second plurality of vias of the second inductor device are drilled or cut vias. 28 . The apparatus of claim 22 , wherein the defined shape is a “C” shape. 29 . The apparatus of claim 22 , wherein the apparatus comprises an embedded three-dimensional (3D) coil. 30 . A non-transitory computer-readable medium storing computer executable code, the code comprising code to: cause a machine to form a plurality of vias on a substrate, wherein code to cause a machine to form each of the plurality of vias comprises code to: cause a machine to plate a first two-dimensional conductive layer on a first side of the substrate, the first two-dimensional conductive layer having a defined shape, cause a machine to plate a second two-dimensional conductive layer on a second side of the substrate, the second two-dimensional conductive layer having the defined shape, and cause a machine to form a via through the substrate to conductively couple the first two-dimensional conductive layer to the second two-dimensional conductive layer; and cause a machine to form a plurality of interconnects to conductively couple the plurality of vias, wherein the first two-dimensional conductive layer and the second two-dimensional conductive layer of each of the plurality of vias are perpendicular to the plurality of interconnects.

Assignees

Inventors

Classifications

  • Package configurations · CPC title

  • the encapsulations exposing the passive side of the semiconductor body · CPC title

  • the substrate having spherical bumps for external connection · CPC title

  • Dispositions, e.g. layouts · CPC title

  • batch processes · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2017372831A1 cover?
Disclosed is an apparatus including a plurality of vias each having a defined shape, wherein each of the plurality of vias includes a first two-dimensional conductive layer plated on a first side of a substrate, the first two-dimensional conductive layer having the defined shape, a second two-dimensional conductive layer plated on a second side of the substrate, the second two-dimensional condu…
Who is the assignee on this patent?
Qualcomm Inc
What technology area does this patent fall under?
Primary CPC classification H01F41/041. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Dec 28 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).