Electronic substrates having embedded inductors
US-2024331921-A1 · Oct 3, 2024 · US
US9196409B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9196409-B2 |
| Application number | US-201113991616-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 5, 2011 |
| Priority date | Dec 6, 2010 |
| Publication date | Nov 24, 2015 |
| Grant date | Nov 24, 2015 |
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In order to reduce the inter-path capacitance of an inductor, an integrated circuit inductor design is provided in which the path crossings are designed such that the voltage differences between the adjacent paths in the loops are (in total) minimized.
Opening claim text (preview).
The invention claimed is: 1. An inductor comprising: a conducting track arranged in two loops that form a figure of eight shape, each loop comprising at least two concentric paths, wherein the track length comprises tap regions at the ends of the tracks and a central track region which comprises the concentric paths of the loops, wherein the central track region comprises a sequence of track sections, each comprising a loop half turn, and crossings between tracks sections, with th…
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