Field effect transistor with heterostructure channel

Patent metadata

Field	Value
Publication number	US-9437738-B2
Application number	US-201414175341-A
Country	US
Kind code	B2
Filing date	Feb 7, 2014
Priority date	Feb 7, 2014
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

In some embodiments, an FET structure comprises a heterostructure, and a gate structure. The heterostructure comprises a first section, a barrier section and a second section such that a portion of the first section, the barrier section, and a portion of the second section form a channel region, and portions of the first section and the second section on opposite sides of the channel region form at least portions of source and drain regions, respectively. When the channel region is p type, the barrier section has a positive valence band offset with respect to each of the first section and the second section, or when the channel region is n type, the barrier section has a positive conduction band offset with respect to each of the first section and the second section. A gate structure is configured over the channel region.

First claim

What is claimed is:

1. A field effect transistor (FET) structure, comprising:
a heterostructure comprising:
a first section, a barrier section and a second section such that a portion of the first section, the barrier section, and a portion of the second section form a channel region, and portions of the first section and the second section on opposite sides of the channel region form at least a portion of a first source or drain region and at least a portion of a second source or drain region, respectively,
a band gap of the barrier section overlapping with a band gap of each of the first section and the second section, and
when the channel region is p type, the barrier section having a positive valence band offset with respect to each of the first section and the second section, or when the channel region is n type, the barrier section having a positive conduction band offset with respect to each of the first section and the second section; and

a gate structure configured over the channel region;
wherein the heterostructure forms a nanowire structure suspended over a surface of a substrate;
wherein:
for the p type channel region,
the barrier section is formed of Si 1-x Ge x , and
the first section and the second section are formed of Si 1-y Ge y , where 0≦x<y≦1; or

for the n type channel region,
the barrier section is formed of Si x Ge 1-x , and

the first section and the second section are formed of Si y Ge 1-y , where 0≦x<y≦1.

2. The FET structure of claim 1 , wherein:
the heterostructure forms at least a portion of a fin structure protruding from the surface of the substrate; and
the gate structure wraps around the channel region.

3. The FET structure of claim 1 , wherein:
the first section and the second section of the hetero structure are strained by a portion of the fin structure beneath the heterostructure; and
the barrier section has the same material as the portion of the fin structure beneath the heterostructure.

4. The FET structure of claim 1 , wherein:
the heterostructure is formed in a layer over a surface of a substrate; and
the gate structure is configured over the channel region.

5. The FET structure of claim 1 , wherein:
the gate structure wraps around the channel region.

6. A field effect transistor (FET) structure, comprising:
a heterostructure comprising:
a first section, a barrier section and a second section such that a portion of the first section, the barrier section, and a portion of the second section form a channel region, and portions of the first section and the second section on opposite sides of the channel region form at least a portion of a first source or drain region and at least a portion of a second source or drain region, respectively,
a band gap of the barrier section overlapping with a band gap of each of the first section and the second section, and
when the channel region is p type, the barrier section having a positive valence band offset with respect to each of the first section and the second section, or when the channel region is n type, the barrier section having a positive conduction band offset with respect to each of the first section and the second section; and

a gate structure configured over the channel region;
wherein the heterostructure forms a nanowire structure suspended over a surface of a substrate;
wherein:
for the p type channel region,
the barrier section is formed of GaAs 1-x Sb x , and
the first section and the section are formed of GaAs 1-y Sb y , where 0≦x<y≦1; or

for the n type channel region,
the barrier section is formed of In x Ga 1-x As, and
the first section and the section are formed of In y Ga 1-y As or GaAs 1-y Sb y , where 0≦x<y≦1.

7. A method, comprising:
providing a first layer;
removing a first section and a second section of the first layer such that a barrier section between the first section and the second section remains;
epitaxially growing a third section and a fourth section in place of the first section and the second section,
a band gap of the barrier section overlapping with a band gap of each of the first section and the second section, and
when the channel region is p type, the barrier section having a positive valence band offset with respect to each of the third section and the fourth section, or when the channel region is n type, the barrier section having a positive conduction band offset with respect to each of the third section and the fourth section; and

forming a gate structure over a portion of the third section, the barrier section, and the fourth section;

wherein:
providing a first layer comprises:
forming a nanowire structure suspended over a surface of a substrate by pad regions,
the nanowire structure comprising the first layer; and

forming a sacrificial gate structure wrapping around a portion of the nanowire structure;

removing a first section and a second section of the first layer comprises:
removing the pad regions and the first section and the second section of the first layer; and

forming a gate structure over a portion of the third section, the barrier section, and the fourth section comprises:
forming a gate structure in place of the sacrificial gate structure.

8. A method, comprising:
providing a first layer;
removing a first section and a second section of the first layer such that a barrier section between the first section and the second section remains;
epitaxially growing a third section and a fourth section in place of the first section and the second section,
a band gap of the barrier section overlapping with a band gap of each of the first section and the second section, and
when the channel region is p type, the barrier section having a positive valence band offset with respect to each of the third section and the fourth section, or when the channel region is n type, the barrier section having a positive conduction band offset with respect to each of the third section and the fourth section; and

forming a gate structure over a portion of the third section, the barrier section, and the fourth section;
wherein:
removing a first section and a second section of the first layer comprises:
forming a hard mask over a portion of the first section, the barrier section and a portion of the second section;
etching portions of the first layer on two sides of the hard mask;
converting the portion of the first section, the portion of the second section into a selectively etchable material with respect to a material of the barrier section; and

etching the converted portion of the first section and the portion of the section.

9. The method of claim 8 , wherein:
providing a first layer comprises:
forming a fin structure protruding from a surface of a substrate,
the fin structure comprising the first layer; and

forming a gate structure over a portion of the third section, the barrier section, and the fourth section comprises:
forming the gate structure wrapping around the portion of the third section, the barrier section, and the portion of the fourth section.

10. The method of claim 8 , wherein:
providing a first layer comprises:
providing a substrate or forming the first layer over a surface of a substrate; and

forming a gate structure over a portion of the third section, the barrier section, and the fourth section comprises:
forming the gate structure over the portion of the third section, the barrier section, and the portion of the fourth section.

11. The method of claim 8 , wherein:
for the p-type channel region,
providing a first layer comprises:
providing the first layer formed of Si 1-x Ge x ; and
epitaxially growing a third section and a fo

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Chien-Ming

Classifications

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D62/123

  comprising junctions · CPC title