Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation

Patent metadata

Field	Value
Publication number	US-9570614-B2
Application number	US-201314914102-A
Country	US
Kind code	B2
Filing date	Sep 27, 2013
Priority date	Sep 27, 2013
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor fin disposed above a semiconductor substrate, the semiconductor fin having a central protruding segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin;
a cladding layer region disposed on the central protruding segment of the semiconductor fin;
a gate stack disposed on the cladding layer region; and
source/drain regions disposed in the pair of protruding outer segments of the semiconductor fin.

2. The semiconductor device of claim 1 , further comprising:
a second cladding layer region disposed on one of the pair of protruding outer segments; and
a third cladding layer region disposed on the other of the pair of protruding outer segments, wherein the second and third cladding regions are discrete from, but contiguous with, the cladding layer region disposed on the central protruding segment of the semiconductor fin.

3. The semiconductor device of claim 1 , wherein the semiconductor fin and the cladding layer region together provide a compliant substrate.

4. The semiconductor device of claim 1 , wherein the central protruding segment is spaced apart from the pair of protruding outer segments by an isolation layer.

5. The semiconductor device of claim 1 , wherein the semiconductor fin consists essentially of silicon, and the cladding layer region consists essentially of germanium.

6. The semiconductor device of claim 4 , wherein the semiconductor device is a PMOS device.

7. The semiconductor device of claim 1 , wherein the semiconductor fin consists essentially of silicon, and the cladding layer region consists essentially of a III-V material.

8. The semiconductor device of claim 7 , wherein the semiconductor device is an NMOS device.

Assignees

• Intel Corp

Inventors

• Pillarisetty Ravi
• Dasgupta Sansaptak
• Goel Niti
• Le Van H
• Radosavljevic Marko
• Dewey Gilbert
• Mukherjee Niloy
• Metz Matthew V
• Rachmady Willy
• Kavalieros Jack T
• Chu-Kung Benjamin
• Kennel Harold W
• Cea Stephen M
• Chau Robert S

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/791

  Arrangements for exerting mechanical stress on the crystal lattice of the channel regions · CPC title

• H10D62/82

  Heterojunctions · CPC title