Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2017301751-A1
Application number	US-201715638012-A
Country	US
Kind code	A1
Filing date	Jun 29, 2017
Priority date	Jun 30, 2015
Publication date	Oct 19, 2017
Grant date	—

Abstract

A semiconductor device includes: a first conductivity type drift region having crystal defects generated by electron-beam irradiation; a first main electrode region of a first conductivity type arranged in the drift region and having an impurity concentration higher than that of the drift region; and a second main electrode region of a second conductivity type arranged in the drift region to be separated from the first main electrode region, wherein the crystal defects contain a first composite defect implemented by a vacancy and oxygen and a second composite defect implemented by carbon and oxygen, and a density of the crystal defects is set so that a peak signal intensity of a level of the first composite defect identified by a deep-level transient spectroscopy measurement is five times or more than a peak signal intensity of a level of the second composite defect.

First claim

1 . A semiconductor device comprising:
a first conductivity type drift region having crystal defects generated by electron-beam irradiation; a first main electrode region of a first conductivity type arranged in a portion of the drift region and having an impurity concentration higher than that of the drift region; and a second main electrode region of a second conductivity type arranged in another portion of the drift region to be separated from the first main electrode region, wherein the crystal defects contain a first composite defect implemented by a vacancy and oxygen and a second composite defect implemented by carbon and oxygen, and a density of the crystal defects is set so that a peak signal intensity of a level of the first composite defect identified by a deep-level transient spectroscopy measurement is five times or more than a peak signal intensity of a level of the second composite defect.

2 . The semiconductor device of claim 1 , further comprising a control-electrode structure configured to control movement of carriers drifting in the drift region.

3 . The semiconductor device of claim 2 , wherein the control-electrode structure includes:
a second conductivity type base region provided at least between the first main electrode region and the drift region; and a gate electrode electrostatically controlling a potential in the base region to control the movement of the carriers.

4 . The semiconductor device of claim 3 , wherein the first main electrode region is arranged on an upper surface of the drift region, and the second main electrode region is arranged on a back surface of the drift region.

5 . The semiconductor device of claim 4 , wherein the control-electrode structure further includes:
a gate insulating film provided on an inner surface of a recess penetrating the base region and reaching an upper portion of the drift region so as to be interposed between the base region; and the gate electrode,
wherein the gate electrode electrostatically control the potential of the base region through the gate insulating film.

6 . The semiconductor device of claim 1 , wherein a ratio of a peak signal intensity of the level of the second composite defect identified by a deep-level transient spectroscopy measurement to an intensity at a valley of curve between a signal peak of the level of the second composite defect and a signal peak of a level of a third composite defect, which is implemented by two vacancies or with two vacancies and oxygen, is set in a range of 1.0 to 1.5, and a ratio of a peak signal intensity of the level of the third composite defect to the intensity at the valley is set in a range of 2.0 to 2.5.

7 . The semiconductor device of claim 1 , wherein a ratio of a peak signal intensity of the level of the second composite defect identified by a deep-level transient spectroscopy measurement to an intensity at a valley of curve between a signal peak of the level of the second composite defect and a signal peak of a level of a third composite defect, which is implemented by two vacancies or with two vacancies and oxygen, is set in a range of 1.6 to 2.0, and a ratio of a peak signal intensity of the level of the third composite defect to the intensity at the valley is set in a range of 2.6 to 3.0.

8 . A method of manufacturing a semiconductor device having a first composite defect implemented by a vacancy and oxygen and a second composite defect implemented by carbon and oxygen, comprising:
forming a first main electrode region of a first conductivity type on a portion of a semiconductor substrate having the first conductivity type, the first main electrode region having an impurity concentration higher than that of the semiconductor substrate; forming a second main electrode region of a second conductivity type on another portion of the semiconductor substrate so as to be separated from the first main electrode region; and generating crystal defects in the semiconductor substrate by irradiating the semiconductor substrate with electron beams, wherein, acceleration energy of the electron beam is set so that a peak signal intensity of a level of the first composite defect identified by a deep-level transient spectroscopy measurement is five times or more than a peak signal intensity of a level of the second composite defect.

9 . The method of claim 8 , wherein the first main electrode region is formed on an upper surface of the semiconductor substrate, and the second main electrode region is formed on a back surface of the semiconductor substrate.

10 . The method of claim 9 , further comprising:
forming a second conductivity type base region between the first main electrode region and the semiconductor substrate; forming a recess penetrating the base region and reaching an upper portion of the semiconductor substrate; forming a gate insulating film on an inner surface of the recess; and burying a gate electrode in the recess through the gate insulating film, the gate electrode controls a potential in the base region.

11 . The method of claim 8 , wherein the acceleration energy of the electron beam is 3 MeV or less.

Assignees

• Fuji Electric Co Ltd

Inventors

• Agata Yasunori
• Takahashi Hidenori
• Mitamura Naoki
• SHIMAMURA Aki
• Ozaki Daisuke

Classifications

• H10P14/6539

  by exposure to corpuscular radiation, e.g. exposure to electrons, alpha-particles, protons or ions · CPC title

• H10P34/40

  with high-energy radiation · CPC title

• H10D8/043

  of planar diodes · CPC title

• H10D8/01

  Manufacture or treatment · CPC title

• H01L29/66348

  Electricity · mapped topic