Semiconductor packages and methods for forming semiconductor package

Patent metadata

Field	Value
Publication number	US-2017294401-A1
Application number	US-201715477170-A
Country	US
Kind code	A1
Filing date	Apr 3, 2017
Priority date	Oct 10, 2013
Publication date	Oct 12, 2017
Grant date	—

Abstract

Semiconductor packages and methods for forming a semiconductor package are presented. The semiconductor package includes a package substrate having a die region on a first surface thereof. The package includes a die having a sensing element. The die is disposed in the die region and is electrically coupled to contact pads disposed on the first surface of the package substrate by insulated wire bonds. A cap is disposed over the first surface of the package substrate. The cap and the first surface of the package substrate define an inner cavity which accommodates the die and the insulated wire bonds. The insulated wire bonds are directly exposed to an environment through at least one access port of the package.

First claim

What is claimed is:

1 . A semiconductor package comprising:
a package substrate, wherein the package substrate comprises a top substrate surface and a bottom substrate surface, wherein the package substrate is defined with a die region and a non-die region surrounding the die region; conductive traces disposed within the package substrate; via contacts disposed within the package substrate and below the conductive traces; a die disposed on the top substrate surface and in the die region, wherein the die comprises die pads and a sensing element disposed on a surface of the die, wherein insulated wire bonds electrically couple the die pads to contact pads disposed on the top substrate surface, wherein each of the insulated wire bonds comprises a conductive wire and a dielectric coating surrounding the conductive wire; a cap disposed over the top substrate surface, wherein the cap and the top substrate surface define an inner cavity which accommodates the die and the insulated wire bonds; at least one access port in communication with an external environment outside of the semiconductor package, wherein the access port exposes the die to the external environment; and package contacts disposed on the bottom substrate surface, wherein the via contacts in the package substrate couple the package contacts to the conductive traces.

2 . The semiconductor package of claim 1 wherein:
the cap comprises a top portion and sidewalls; and
the access port extends through inner and outer surfaces of the top portion of the cap, wherein the access port is disposed directly above the sensing element of the die.

3 . The semiconductor package of claim 2 wherein the top portion of the cap comprises a transparent material and the sidewalls of the cap comprises a dielectric material.

4 . The semiconductor package of claim 1 comprising a stud bump disposed on each die pad, wherein a first end of each of the insulated wire bonds is coupled to the contact pad by a ball bond and a second end of each of the insulated wire bonds is coupled to the stud bump by a stitch bond.

5 . The semiconductor package of claim 4 further comprising a protective layer covering the first and second ends of each of the insulated wire bonds, wherein the protective layer covers the ball bond and the stitch bond.

6 . The semiconductor package of claim 1 wherein the package substrate comprises a printed circuit board substrate.

7 . The semiconductor package of claim 1 wherein:
the cap comprises a top portion and sidewalls; and
the access port extends through inner and outer surfaces of the sidewalls of the cap.

8 . The semiconductor package of claim 7 comprising a dielectric sealing ring disposed on the die and surrounding the sensing element, wherein a semiconductor lid is attached to a top surface of the dielectric sealing ring, wherein the semiconductor lid, the dielectric sealing ring and the die define a cavity which accommodates the sensing element.

9 . The semiconductor package of claim 1 wherein the access port extends through the top and bottom surfaces the package substrate.

10 . The semiconductor package of claim 9 wherein the die comprises a recess disposed in an inactive region of the die, wherein the sensing element is disposed within the recess and directly above the access port in the package substrate.

11 . The semiconductor package of claim 1 comprising a non-conductive stiffener disposed within the package substrate, wherein the non-conductive stiffener is disposed below the conductive traces.

12 . The semiconductor package of claim 11 wherein the package substrate comprises a first dielectric layer, wherein the first dielectric layer is disposed between the conductive traces and isolates one conductive trace from another conductive trace, wherein the stiffener is disposed below the first dielectric layer.

13 . The semiconductor package of claim 12 wherein the package substrate comprises a second dielectric layer, wherein the second dielectric layer is disposed between the via contacts and isolates one via contact from another via contact, wherein at least one of the via contacts extends beyond a bottom of the second dielectric layer.

14 . The semiconductor package of claim 13 wherein the package substrate comprises a patterned leadframe, wherein the patterned leadframe defines the conductive traces and the via contacts, wherein the first and second dielectric layers of the package substrate is disposed within recesses of the patterned leadframe.

15 . A semiconductor package comprising:
a package substrate, wherein the package substrate comprises a top and a bottom substrate surface, wherein the package substrate is defined with a die region and a non-die region surrounding the die region; conductive traces disposed within the package substrate; via contacts disposed within the package substrate and below the conductive traces, wherein the via contacts are coupled to a bottom of the conductive traces; a non-conductive stiffener disposed within the package substrate, wherein the non-conductive stiffener is disposed below the conductive traces; a die disposed on the top substrate surface and in the die region, wherein the die comprises a sensing element disposed on a surface of the die; insulated wire bonds electrically coupling the die to the conductive traces in the package substrate, wherein each insulated wire bond comprises a conductive wire and an insulator layer surrounding the conductive wire, wherein the insulator layer covers and extends along a length of each conductive wire; a cap disposed on the package substrate, wherein the cap and the top substrate surface define an inner cavity which accommodates the die and wire bonds; and package contacts disposed on the bottom substrate surface, wherein the via contacts in the package substrate couple the package contacts to the conductive traces.

16 . The semiconductor package of claim 15 wherein the package substrate comprises a patterned leadframe, wherein the patterned leadframe defines the conductive traces and the via contacts.

17 . The semiconductor package of claim 16 wherein the package substrate comprises a first and a second dielectric layer, wherein the first dielectric layer is disposed in recesses between the conductive traces and isolates one conductive trace from another conductive trace, wherein the second dielectric layer is disposed in recesses between the via contacts and isolates one via contact from another via contact, wherein at least one of the via contacts extend beyond a bottom of the second dielectric layer.

18 . The semiconductor package of claim 15 wherein:
the sensing element is disposed on an active surface of the die; and
the cap comprises an opening disposed directly above the sensing element, wherein the opening in the cap exposes the sensing element to an external environment outside of the cap.

19 . The semiconductor package of claim 15 wherein:
the package substrate comprises an opening extending through the top and bottom substrate surfaces, wherein the cap is devoid of an opening; and
the die comprises a recess disposed in an inactive region of the die, wherein the sensing element is disposed within the recess of the die and directly above the opening in the package substrate, wherein the opening exposes the sensing element to an external environment outside of the package substrate.

20 . The semiconductor package of claim 15 wherein the die comprises die pads and a passivation lay

Assignees

• Utac Headquarters Pte Ltd

Inventors

• Suthiwongsunthorn Nathapong
• Beleran John Ducyao
• Pedron Jr Serafin Padilla

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/5525

  comprising copper [Cu] · CPC title