Lead-free solder bump joining structure

Patent metadata

Field	Value
Publication number	US-2017259366-A1
Application number	US-201515529637-A
Country	US
Kind code	A1
Filing date	Oct 30, 2015
Priority date	Nov 27, 2014
Publication date	Sep 14, 2017
Grant date	—

Abstract

In a lead-free solder bump, diffusion of Cu from intermetallic compound layers, which are respectively formed at joining interfaces with Cu electrodes is suppressed, so that the in metallic compound layers are not likely to disappear. Correspondingly, with the use of the intermetallic compound layers, Cu is not likely to diffuse from the Cu electrodes into the lead-free solder bump. Even when an electric current flows continuously between a first electronic member and a second electronic member through the lead-free solder bump, the occurrences of the electromigration phemenon and the thermomigration phenomenon are suppressed. Thus, the present invention provides a lead-free solder bump joining structure capable of suppressing the disconnection failure caused by the synergistic effect of the electromigration phenomenon and the thermomigration phenomenon.

First claim

1 - 9 . (canceled)

10 . A lead-free solder bump joining structure that joins a first copper electrode of a first electronic device and a second copper electrode of a second electronic device, thereby to allow electric current to flow therebetween at an electric current density of 0.7×10 3 [A/cm 2 ] or more, the lead-free solder bump joining structure comprising:
a lead-free solder bump containing any one or any two or more of Ni, Co, Pd, Au and Pt at 0.03 to 0.32% by mass in total and a balance of Sn and inevitable impurities; and
a first interfacial layer disposed between the lead-free solder bump and the first copper electrode; and
a second interfacial layer disposed between the lead-free solder bump and the second copper electrode,
wherein the first and the second interfacial layers are formed of an intermetallic compound expressed by a molecular formula (Cu, X) 6 Sn 5 , wherein X indicates any one or any two or more of Ni, Co, Pd, Au and Pt, and have an average thickness of 0.4 [μm] or more and 1.2 [μm] or less.

11 . The lead-free solder bump joining structure according to claim 10 , wherein the X includes Ni and any one or any two or more of Co, Pd, Au and Pt.

12 . The lead-free solder bump joining structure according to claim 10 , wherein the X is any one or any two or more of Co, Pd, Au and Pt and excludes Ni.

13 . The lead-free solder bump joining structure according to claim 10 , wherein the lead-free solder bump includes any one or any two or more of Ag, Cu and Bi in a content of 0.1 to 7.0% by mass in total.

14 . The lead-free solder bump joining structure according to claim 10 , wherein the lead-free solder bump further includes any one or any two of Mg, P and Ge in a content of 0.0001 to 0.108% by mass in total.

15 . The lead-free solder bump joining structure according to claim 10 , wherein a content of Fe in the lead-free solder bump is equal to or less than a detection limit of ICP (Inductively Coupled. Plasma) analysis.

16 . The lead-free solder bump joining structure according to claim 10 , wherein the Sn is a low α-ray Sn that emits α-rays at an α-ray dose of 1 [cph/cm 2 ] or less.

17 . The lead-free solder bump joining according to claim 10 , wherein the X is any one or two of Au and Pt,

Assignees

• Nippon Steel & Sumikin Mat Co
• Nippon Micrometal Corp

Inventors

• Ishikawa Shinji
• Terashima Shinichi
• Akashi Keisuke

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title