Semiconductor devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2017200718-A1
Application number	US-201615384834-A
Country	US
Kind code	A1
Filing date	Dec 20, 2016
Priority date	Jan 11, 2016
Publication date	Jul 13, 2017
Grant date	—

Abstract

A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgassing prevention pattern sequentially stacked.

First claim

1 . A semiconductor device, comprising:
an active fin on a substrate; a gate structure on the active fin; a gate spacer structure on a sidewall of the gate structure, the gate spacer structure including a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgassing prevention pattern sequentially stacked; and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure.

2 . The semiconductor device of claim 1 , wherein the wet etch stop pattern and the outgassing prevention pattern include silicon carbonitride and silicon nitride, respectively.

3 . The semiconductor device of claim 1 , wherein the oxygen-containing silicon pattern includes silicon oxycarbonitride, silicon dioxide and/or silicon oxynitride.

4 . The semiconductor device of claim 3 , wherein the oxygen-containing silicon pattern includes silicon oxycarbonitride, and wherein the outgassing prevention pattern prevents a component of the oxygen-containing silicon pattern from outgassing.

5 . The semiconductor device of claim 1 , further comprising a diffusion prevention pattern on the wet etch stop pattern, the diffusion prevention pattern preventing a component of the wet etch stop pattern from diffusing into the active fin.

6 .- 8 . (canceled)

9 . The semiconductor device of claim 1 , wherein at least one of the wet etch stop pattern and the oxygen-containing silicon pattern has a cross-section taken along a direction, the cross-section having an L-like shape.

10 . (canceled)

11 . The semiconductor device of claim 1 , wherein the wet etch stop pattern directly contacts the sidewall of the gate structure.

12 .- 16 . (canceled)

17 . The semiconductor device of claim 1 , wherein the source/drain layer includes silicon-germanium, silicon carbide, or silicon.

18 . The semiconductor device of claim 1 , wherein the active fin extends in a first direction substantially parallel to an upper surface of the substrate, the gate structure extends in a second direction crossing the first direction, and the gate spacer structure is formed on at least one of opposite sidewalls of the gate structure in the first direction.

19 . (canceled)

20 . The semiconductor device of claim 1 , wherein the outgassing prevention pattern prevents a component of the oxygen-containing silicon pattern from outgassing.

21 . A semiconductor device, comprising:
first and second active fins on first and second regions, respectively, of a substrate; first and second gate structures on the first and second active fins, respectively; a first gate spacer structure on a sidewall of the first gate structure, the first gate spacer structure including a first wet etch stop pattern, a first oxygen-containing silicon pattern, and a first outgassing prevention pattern sequentially stacked; a second gate spacer structure on a sidewall of the second gate structure, the second gate spacer structure including a second wet etch stop pattern, a second oxygen-containing silicon pattern, and a second outgassing prevention pattern sequentially stacked; a first second source/drain layer on at least a portion of the first active fin adjacent the first gate spacer structure; and a second source/drain layer on at least a portion of the second active fin adjacent the second gate spacer structure.

22 . The semiconductor device of claim 21 , wherein the first source/drain layer includes silicon-germanium, and the second source/drain layer includes silicon carbide or silicon.

23 .- 28 . (canceled)

29 . The semiconductor device of claim 21 , wherein the first and second wet etch stop patterns include silicon carbonitride, and the first and second outgassing prevention patterns include silicon nitride.

30 . The semiconductor device of claim 21 , wherein the first and second oxygen-containing silicon patterns include silicon oxycarbonitride, silicon dioxide and/or silicon oxynitride.

31 . The semiconductor device of claim 21 , further comprising:
first and second diffusion prevention patterns on the first and second wet etch stop patterns, respectively, the first and second diffusion prevention patterns configured to prevent components of the respective first and second wet etch stop patterns from diffusing into the first and second active fins, respectively.

32 .- 57 . (canceled)

58 . A semiconductor structure, comprising:
at least one active fin on a substrate; a gate structure on the at least one active fin; a gate spacer structure on a sidewall of the gate structure, the gate spacer structure being configured to reduce outgassing of carbon; and a source/drain layer on at least a portion of the at least one active fin adjacent the gate spacer structure.

59 . The semiconductor structure of claim 58 , wherein the gate spacer structure is a multilayered structure that comprises at least a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgassing reduction pattern in a stacking configuration.

60 . The semiconductor structure of claim 59 , wherein the oxygen-containing silicon pattern comprises at least one of a silicon oxycarbonitride layer, a silicon dioxide layer and a silicon oxynitride layer.

61 . The semiconductor structure of claim 59 , wherein the wet etch stop pattern and the outgassing prevention pattern comprise at least a silicon carbonitride layer and at least a silicon nitride layer, respectively.

62 . The semiconductor structure of claim 58 , wherein the at least one active fin comprises:
a first active fin on a first region of the substrate; and a second active fin on a second region of the substrate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Sung-Hyun
• Tak Yong-Suk
• Park Gi-Gwan
• Koo Bon-Young
• Park Ki-Yeon
• Seo Won-Oh

Classifications

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

• H10W76/48

  Fillings including materials for absorbing or reacting with moisture or other undesired substances · CPC title

• H01L29/1608

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L21/823418

  Electricity · mapped topic