Methods of forming reduced thickness spacers in CMOS based integrated circuit products

Patent metadata

Field	Value
Publication number	US-9385124-B1
Application number	US-201514845499-A
Country	US
Kind code	B1
Filing date	Sep 4, 2015
Priority date	Sep 4, 2015
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

One method disclosed herein includes, among other things, forming a first spacer proximate gate structures of first and second transistors that are opposite type transistors, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, performing a timed, wet etching process on both of the transistors so as to completely remove the layer of second spacer material from the second transistor while leaving a reduced thickness second spacer positioned adjacent the first spacer of the first transistor, wherein the reduced thickness second spacer has a thickness that is less than an initial thickness of the initial second spacer, and forming a third spacer on and in contact with the first spacer of the second transistor.

First claim

What is claimed:

1. A method of forming a CMOS integrated circuit product comprised of a first transistor of a first type and a second transistor of a second type formed on a substrate, wherein said second type is opposite to said first type, the method comprising:
forming a first gate structure for said first transistor and a second gate structure for said second transistor;
forming a first spacer proximate both said first and second gate structures;
forming an initial second spacer proximate said first spacer of said first transistor and a layer of second spacer material above said second transistor, said initial second spacer having an initial thickness;
performing a first timed, wet etching process on both said first transistor and said second transistor so as to completely remove said layer of second spacer material from said second transistor and thereby expose said first spacer of said second transistor while leaving a first reduced thickness second spacer positioned adjacent said first spacer of said first transistor, wherein said first reduced thickness second spacer has a thickness that is less than said initial thickness of said initial second spacer; and
forming a third spacer for said second transistor on and in contact with said first spacer of said second transistor.

2. The method of claim 1 , wherein forming said initial second spacer proximate said first spacer of said first transistor comprises forming said initial second spacer on and in contact with said first spacer of said first transistor.

3. The method of claim 1 , wherein forming said first spacer comprises forming said first spacer from a material having a k value less than 7.8.

4. The method of claim 3 , wherein forming said initial second spacer comprises forming said initial second spacer from silicon nitride.

5. The method of claim 4 , wherein forming said third spacer comprises forming said third spacer from silicon nitride.

6. The method of claim 1 , wherein said first spacer is comprised of SiCON and said initial second spacer and said third spacer are comprised of silicon nitride.

7. The method of claim 1 , wherein said initial second spacer is made of silicon nitride and wherein performing said first timed wet etching process on said initial second spacer of said first transistor comprises performing said first timed wet etching process using H 3 PO 4 as an etchant.

8. The method of claim 1 , wherein said thickness of said first reduced thickness second spacer is 30-50% of said initial thickness of said initial second spacer on said first transistor.

9. The method of claim 1 , wherein, after forming said initial second spacer on said first transistor, and prior to performing said first timed wet etching process, the method further comprises:
forming a plurality of first source/drain cavities in said substrate adjacent said first gate structure, wherein an uppermost inner edge of said first source/drain cavities are self-aligned with said initial second spacer in said first transistor; and
forming a first epi semiconductor material in said first source/drain cavities.

10. The method of claim 9 , wherein, after forming said third spacer, the method further comprises:
forming a plurality of second source/drain cavities in said substrate adjacent said second gate structure, wherein an uppermost inner edge of said second source/drain cavities are self-aligned with said third spacer in said second transistor; and
forming a second epi semiconductor material in said second source/drain cavities.

11. The method of claim 1 , wherein forming said third spacer for said second transistor comprises forming a reduced thickness third spacer for said second transistor by performing a method that comprises:
forming a layer of third spacer material above said first and second transistors;
forming an etch mask layer that covers said layer of third spacer material positioned above said first transistor;
with said etch mask in position, performing an etching process to define an initial third spacer for said second transistor that has an initial thickness;
removing said etch mask layer; and
performing a second timed, wet etching process on both said first transistor and said second transistor so as to completely remove said layer of third spacer material from said first transistor and thereby expose said first reduced thickness second spacer of said first transistor while leaving a second reduced thickness third spacer positioned adjacent said first spacer of said second transistor, wherein said reduced thickness third spacer has a thickness that is less than said initial thickness of said initial third spacer.

12. The method of claim 1 , wherein said first transistor is a PMOS transistor and said second transistor is an NMOS transistor.

13. A method of forming a CMOS integrated circuit product comprised of a first transistor of a first type and a second transistor of a second type formed on a substrate, wherein said second type is opposite to said first type, comprising:
forming a first gate structure for said first transistor and a second gate structure for said second transistor;
forming a first spacer proximate both of said first and second gate structures, wherein said first spacer is made of a material having a k value that is less than 7.8;
forming an initial second spacer on and in contact with said first spacer of said first transistor and a layer of second spacer material above said second transistor, wherein said initial second spacer has an initial thickness and is made of silicon nitride;
performing a first timed wet etching process on said first transistor and said second transistor so as to completely remove said layer of second spacer material from said second transistor and thereby expose said first spacer of said second transistor while leaving a reduced thickness second spacer positioned adjacent said first spacer of said first transistor, wherein said reduced thickness second spacer has a thickness that is 30-50% of said initial thickness of said initial second spacer of said first transistor; and
forming a third spacer made of silicon nitride on and in contact with said first spacer of said second transistor.

14. The method of claim 13 , wherein performing said first timed wet etching process on said initial second spacer comprises performing said first timed wet etching process using H 3 PO 4 as an etchant.

15. The method of claim 13 , wherein, after forming said initial second spacer on said first transistor, and prior to performing said first timed wet etching process, the method further comprises:
forming a plurality of first source/drain cavities in said substrate adjacent said first gate structure, wherein an uppermost inner edge of said first source/drain cavities are self-aligned with said initial second spacer in said first transistor; and
forming a first epi semiconductor material in said first source/drain cavities.

16. The method of claim 15 , wherein, after forming said third spacer, the method further comprises:
performing an etching process to form a plurality of second source/drain cavities in said substrate adjacent said second gate structure, wherein an uppermost inner edge of said second source/drain cavities are self-aligned with said third spacer in said second transistor; and
forming a second epi semiconductor material in said second source/drain cavities.

17. The method of claim 13 , wherein forming said third spacer for said second transistor comprises forming a reduced thickness third spacer for said second transistor by performing a method tha

Assignees

• Globalfoundries Inc

Inventors

• Peng Wen Pin
• Chi Min-Hwa
• Derderian Garo Jacques

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6927

  the material being a silicon oxynitride, e.g. SiON or SiON:H · CPC title

• H10D84/8316

  the IGFETs characterised by having gate sidewall spacers specially adapted for integration · CPC title