Time to digital converter, phase difference pulse generator, radio communication device, and radio communication method

Patent metadata

Field	Value
Publication number	US-2017194972-A1
Application number	US-201715462288-A
Country	US
Kind code	A1
Filing date	Mar 17, 2017
Priority date	Dec 25, 2014
Publication date	Jul 6, 2017
Grant date	—

Abstract

A time to digital converter has a counter to measure the number of cycles of a first signal, a first phase difference detector to generate a phase difference signal having a pulse width corresponding to a phase difference, a first capacitor to be charged with an electric charge, a second capacitor including capacitance N times the capacitance of the first capacitor, the N being a real number larger than 1, a comparator to compare a charge voltage of the first capacitor and a charge voltage of the second capacitor, a first charge controller to continue to charge the second capacitor until the comparator detects that the charge voltage of the second capacitor has reached the charge voltage of the first capacitor or more, and a first phase difference arithmetic unit to operate the phase difference between the first signal and the second signal.

First claim

1 . A time to digital converter comprising:
a counter to measure the number of cycles of a first signal; a first phase difference detector to generate a phase difference signal having a pulse width corresponding to a phase difference between the first signal and a second signal having a frequency twice or more lower than the frequency of the first signal; a first capacitor to be charged with an electric charge corresponding to the pulse width of the phase difference signal; a second capacitor including capacitance N times the capacitance of the first capacitor, the N being a real number larger than 1; a comparator to compare a charge voltage of the first capacitor and a charge voltage of the second capacitor; a first charge controller to continue to charge the second capacitor until the comparator detects that the charge voltage of the second capacitor has reached the charge voltage of the first capacitor or more; and a first phase difference arithmetic unit to operate the phase difference between the first signal and the second signal, based on a value obtained by dividing a count value of the counter during a period of the charge to the second capacitor by the N.

2 . The time to digital converter according to claim 1 , further comprising:
a first current source to supply a charge current to the first capacitor and the second capacitor; a first selector to switch whether the charge current is supplied from the first current source to the first capacitor, due to the phase difference signal; and a second selector to switch whether the charge current is supplied from the first current source to the second capacitor, due to a signal from the first charge controller.

3 . The time to digital converter according to claim 1 , further comprising:
a discharge controller to discharge the first capacitor and the second capacitor when the comparator detects that the charge voltage of the second capacitor has reached the charge voltage of the first capacitor or more.

4 . The time to digital converter according to claim 3 ,
wherein the discharge controller comprises:
a third selector to make a short circuitry between both electrodes of the first capacitor so as to discharge the first capacitor, due to a signal from the first charge controller; and
a fourth selector to make a short circuitry between both electrodes of the second capacitor so as to discharge the second capacitor, due to the signal from the first charge controller.

5 . The time to digital converter according to claim 1 ,
wherein the first charge controller charges the first capacitor during time corresponding to the pulse width of the phase difference signal.

6 . The time to digital converter according to claim 1 , further comprising:
a first retaining unit to retain the count value of the counter at a point in time when the charge of the second capacitor is started; a second retaining unit to retain the count value of the counter at a point in time when the comparator detects that the charge voltage of the second capacitor has reached the charge voltage of the first capacitor or more; and a difference arithmetic unit to operate a count value of a difference between the count value of the second retaining unit and the count value of the first retaining unit, wherein the first phase difference arithmetic unit divides the count value operated by the difference arithmetic unit, by the N so as to operate the phase difference.

7 . The time to digital converter according to claim 1 ,
wherein the first phase difference detector comprises:
first synchronizing circuitry to synchronize the second signal at a rising edge or falling edge of the first signal;
m-staged second synchronizing circuitry coupled in series, the m-staged second synchronizing circuitry to latch an output signal of the first synchronizing circuitry or an output signal at a front stage, at the same rising edge or falling edge of the first signal as the first synchronizing circuitry, the m being an integer of 1 or more; and
a first logic and arithmetic unit to generate the phase difference signal based on the output signal of the first synchronizing circuitry and an output signal of the second synchronizing circuitry.

8 . The time to digital converter according to claim 7 , further comprising:
a precharge signal generator to generate a precharge signal having a pulse width corresponding to time necessary for passing the second signal through the m-staged second synchronizing circuitry; and a charge reinforcing unit to reinforce a charge current to the second capacitor during time corresponding to the pulse width of the precharge signal after the charge to the second capacitor is started.

9 . The time to digital converter according to claim 8 ,
wherein the precharge signal generator comprises:
the m-staged third synchronizing circuitry to latch the output of the first synchronizing circuitry or the output at the front stage, at the same rising edge or falling edge of the first signal as the first synchronizing circuitry; and
a second logic and arithmetic unit to generate the precharge signal, based on the output signal of the first synchronizing circuitry and an output signal of the third synchronizing circuitry.

10 . The time to digital converter according to claim 8 , further comprising:
a first current source to supply a charge current to the first capacitor and the second capacitor, wherein the charge reinforcing unit comprises a second current source that supplies the charge current to the second capacitor, and the charge current supplied from the second current source to the second capacitor is K times the charge current supplied from the first current source to the second capacitor, the K being a real number more than 1 and smaller than the N.

11 . The time to digital converter according to claim 1 , further comprising:
a second phase difference detector to generate a phase difference signal having a pulse width corresponding to the phase difference between the first signal and the second signal at a point in time when the comparator detects that the charge voltage of the second capacitor has reached the charge voltage of the first capacitor or more due to the continuous charge of the first charge controller to the second capacitor; a second charge controller to continue to charge the second capacitor until the comparator again detects that the charge voltage of the second capacitor has reached the charge voltage of the first capacitor or more after the first capacitor is charged based on the pulse width of the phase difference signal detected by the second phase difference detector; a second phase difference arithmetic unit to operate the phase difference between the first signal and the second signal, with a value obtained by dividing the count value of the counter during the period of the charge to the second capacitor, by the N squared; and a third phase difference arithmetic unit to detect a decimal phase difference between the first signal and the second signal, based on the phase difference operated by the first phase difference arithmetic unit and the phase difference operated by the second phase difference arithmetic unit.

12 . The time to digital converter according to claim 1 , further comprising:
an integrated circuitry including the counter, the first phase difference detector, the first capacitor, the second capacitor, the comparator, the first charge controller, and the first phase difference arithmetic unit.

13 . The time to digital converter according to claim 12 , further comprising:
the integrated circuitry; and at least one antenna.

Assignees

• Toshiba Kk

Inventors

• Sai Akihide
• Furuta Masanori
• Itakura Tetsuro
• Kondo Satoshi
• Okuni Hidenori
• Ta Tuan Thanh

Classifications

• H03K21/02

  Input circuits · CPC title

• H03K5/24

  the characteristic being amplitude · CPC title

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title