Use of redundancy in sub-ranging time-to-digital converters to eliminate offset mismatch issues

Patent metadata

Field	Value
Publication number	US-9804573-B1
Application number	US-201615394454-A
Country	US
Kind code	B1
Filing date	Dec 29, 2016
Priority date	Dec 29, 2016
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A time-to-digital converter utilizes both coarse and fine quantizers and addresses mismatch by using redundant bits in the coarse time representation and the fine time representation. The redundant bits are compared and if the redundant bits are the same, no mismatch correction is required but if the redundant bits are different a correction is applied to correct the redundant portion of the coarse time information. The redundant portion includes the most significant bit generated by the fine quantizer and the least significant bit of the coarse quantizer. The correction adds to or subtracts from the redundant information.

First claim

What is claimed is:

1. An apparatus comprising:
a fine time-to-digital converter (TDC) providing fine time information with a first resolution, wherein the fine TDC is configured to roll over from a maximum value to a minimum value;
a coarse TDC providing coarse time information with a second resolution, the second resolution more coarse than the first resolution and the second resolution is less than a range of the fine TDC such that a first portion of the fine time information and a second portion of the coarse time information overlap and provide redundancy;
a compare circuit to compare the first portion of the fine time information and the second portion of the coarse time information and supply a mismatch indication in response to the first portion and the second portion not matching; and
a correction circuit to correct the second portion responsive to the mismatch indication.

2. The apparatus as recited in claim 1 , wherein the correction circuit adds to or subtracts from the second portion responsive to the compare circuit supplying the mismatch indication.

3. The apparatus as recited in claim 1 , wherein the correction circuit adds to the second portion if the second portion transitions late with respect to the first portion and the correction circuit subtracts from the second portion if the second portion transitions early with respect to the first portion.

4. The apparatus as recited in claim 2 , wherein an overlapping portion formed by the first portion and the second portion corresponds to a value of N, where N is an integer.

5. The apparatus as recited in claim 1 , wherein the first portion is a most significant bit of the fine time information and the second portion is a least significant bit of the coarse time information.

6. The apparatus as recited in claim 5 wherein the correction circuit adds to or subtracts from the least significant bit responsive to the compare circuit supplying the mismatch indication.

7. The apparatus as recited in claim 6 , wherein the correction circuit adds a one to the least significant bit responsive to the compare circuit supplying the mismatch indication and a second most significant bit of the fine time information is a zero.

8. The apparatus as recited in claim 6 , wherein the correction circuit subtracts a one from the least significant bit responsive to the compare circuit supplying the mismatch indication and a second most significant bit of the fine time information is a one.

9. The apparatus as recited in claim 2 , wherein the fine time information and the coarse time information are concatenated after the correction circuit.

10. The apparatus as recited in claim 1 further comprising a phase generator wherein the phase generator provides N phases, N being an integer of at least four and the fine time information represents one of the N phases and the fine time information rolls over to zero when the fine time information goes from an Nth phase to a first phase of the N phases and wherein the fine time-to-digital converter quantizes a time of an arrival of an edge of a signal using the N phases.

11. A method comprising:
providing fine time information from a fine time-to-digital converter that rolls over from a maximum value to a minimum value;
providing coarse time information from a coarse time-to-digital converter;
comparing a first portion of the fine time information and a second portion of the coarse time information and supplying a mismatch indication in response to the first portion and the second portion not being equal, wherein the first portion and the second portion overlap; and
correcting the second portion responsive to the mismatch indication.

12. The method as recited in claim 11 , wherein the first and second portions correspond to a value of N, where N is an integer.

13. The method as recited in claim 11 , wherein the correcting further comprises adding to or subtracting from the second portion responsive to the mismatch indication.

14. The method as recited in claim 11 , wherein the first portion is a most significant bit of the fine time information and the second portion is a least significant bit of the coarse time information.

15. The method as recited in claim 11 , wherein the correcting further comprises adding to or subtracting from a least significant bit of the coarse time information responsive to the mismatch indication.

16. The method as recited in claim 15 , further comprising adding a one to the least significant bit responsive to the mismatch indication and a second most significant bit of the fine time information being a zero.

17. The method as recited in claim 15 , further comprising subtracting a one from the least significant bit responsive to the mismatch indication and a second most significant bit of the fine time information being a one.

18. The method as recited in claim 15 , further comprising concatenating the fine time information and the coarse time information after correction to the coarse time information.

19. The method as recited in claim 11 , further comprising:
generating the fine time information by quantizing a time of arrival of an edge of a signal with respect to a plurality of phases of a clock signal.

20. A sub-ranging time-to-digital converter comprising:
a fine time-to-digital converter providing fine time information;
a coarse time-to-digital converter providing coarse time information;
a compare circuit to compare a most significant bit of the fine time information and a least significant bit of the coarse time information and supply a mismatch indication in response to the most significant bit and the least significant bit not being equal, wherein the most significant bit and the least significant bit overlap and provide redundancy; and
a correction circuit to correct the least significant bit of the coarse time information responsive to the mismatch indication.

Assignees

• Silicon Lab Inc

Inventors

• Drost Brian G
• Roy Ankur Guha

Classifications

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03M1/16

  with scale factor modification, i.e. by changing the amplification between the steps {(H03M1/141 takes precedence)} · CPC title

• H03M1/188

  Multi-path, i.e. having a separate analogue/digital converter for each possible range · CPC title

• H03M1/0692 Primary

  using a diminished radix representation, e.g. radix 1.95 · CPC title

• H03M1/60

  with intermediate conversion to frequency of pulses · CPC title