High resolution time-to-digital convertor

Patent metadata

Field	Value
Publication number	US-9811056-B2
Application number	US-201715422523-A
Country	US
Kind code	B2
Filing date	Feb 2, 2017
Priority date	Apr 17, 2015
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A circuit includes a time delta detector configured to receive an input clock signal and a reference clock signal and generate a delta pulse signal and a reference pulse signal. A comparison circuit is configured to receive the delta pulse signal and the reference pulse signal. The comparison circuit generates an output indicative of a bit of a time difference between the input clock signal and the reference clock signal. A control circuit is configured to receive the output from the comparison circuit. The control circuit maintains a count of the time difference between the input clock signal and the reference clock signal.

First claim

What is claimed is:

1. A circuit, comprising:
a pulse generator configured to receive an input clock signal and a reference clock signal and generate a delta pulse signal;
a spatial division multiplexing circuit configured to receive the delta pulse signal and the reference clock signal and generate an output indicative of a time difference between the input clock signal and the reference clock signal; and
a counter configured to maintain a count representing the time difference between the input clock signal and the reference clock signal.

2. The circuit of claim 1 , wherein the spatial division multiplexing circuit comprises at least one convertor circuit and at least one quantizer circuit.

3. The circuit of claim 2 , wherein the at least one convertor circuit comprises a charging source coupled to a first side of a switch and a capacitor coupled to a second side of the switch, wherein the switch is controlled by a pulse generated by the pulse generator, and wherein the at least one convertor circuit generates an output voltage.

4. The circuit of claim 3 , wherein the at least one convertor circuit comprises a dump switch coupled to the second side of the switch and the capacitor, wherein the dump switch is configured to discharge the capacitor.

5. The circuit of claim 3 , wherein the charging source is a current source.

6. The circuit of claim 2 , wherein the at least one convertor circuit comprises a first convertor circuit and a second convertor circuit, wherein the first convertor circuit is controlled by a delta pulse generated by the pulse generator, and wherein the second convertor circuit is controlled by an input pulse.

7. The circuit of claim 6 , wherein the at least one quantizer comprises a first source and a second source, wherein the first source generates an input current based on an output of the first convertor circuit and the second source generates an input current based on an output of the second convertor circuit.

8. The circuit of claim 7 , wherein the quantizer comprises a comparator configured to receive a first input voltage and a second input voltage, wherein the first input voltage is generated by a capacitor coupled to the first source and the second source.

9. The circuit of claim 8 , wherein the second input voltage of the comparator comprises a reference voltage.

10. The circuit of claim 8 , wherein the reference clock signal is provided to the comparator as a reset signal.

11. The circuit of claim 1 , wherein the pulse generator comprises a time delta detector.

12. The circuit of claim 11 , wherein the time delta detector generates the delta pulse signal and the reference pulse signal based on state changes of the input clock signal and the reference clock signal.

13. The circuit of claim 11 , wherein the time delta detector comprises a reference frequency predictor.

14. The circuit of claim 11 , wherein the time delta detector is configured to generate a polarity signal, a dump pulse, and a delayed reference clock signal.

15. A method of time-to-digital conversion, the method comprising:
receiving an input clock signal and a reference clock signal;
generating a delta pulse signal from the input clock signal and the reference clock signal;
coupling a first capacitor to a first source during a first period defined by the delta pulse signal;
coupling a second capacitor to a second source during a second period defined by the input clock signal; and
comparing a total voltage generated by the first and second capacitors to a reference voltage; and
incrementing a count representative of a time difference between the input signal and the reference clock signal based on the total voltage.

16. The method of claim 15 , wherein the first capacitor is coupled to the first source by a first switch configured to receive the delta pulse signal and the second capacitor is coupled to the second source by a second switch configured to receive the input clock signal.

17. The method of claim 15 , wherein the total voltage is generated by coupling the first and second capacitors to a third capacitor, and wherein the third capacitor is charged by a voltage difference between the first and second capacitors.

18. A circuit, comprising:
a pulse generator configured to receive an input clock signal and a reference clock signal and generate a delta pulse signal and an input pulse signal;
a spatial division multiplexing circuit configured to receive the delta pulse signal and the input pulse signal and generate an output indicative of a time difference between the input clock signal and the reference clock signal; and
a counter configured to maintain a count representative of the time difference between the input clock signal and the reference clock signal.

19. The circuit of claim 18 , wherein the spatial division multiplexing circuit comprises a first convertor circuit configured to receive the delta pulse signal and generate a delta voltage output and a second convertor circuit configured to receive the input pulse signal and generate an input voltage output.

20. The circuit of claim 19 , wherein each of the first and second convertor circuits comprise a charging source coupled to a first side of a switch and a capacitor coupled to a second side of the switch, wherein the switch is controlled by one of the delta pulse signal or the input pulse signal.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cho Lan-Chou
• Jou Chewn-Pu
• Kuo Feng-Wei
• Chen Huan-Neng

Classifications

• H03K2005/00058

  controlled by a digital setting · CPC title

• H03K5/131

  Digitally controlled · CPC title

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03K2005/00071

  by adding capacitance as a load · CPC title

• H03K5/135

  by the use of time reference signals, e.g. clock signals · CPC title