Devices Employing Thermal and Mechanical Enhanced Layers and Methods of Forming Same

Patent metadata

Field	Value
Publication number	US-2017194292-A1
Application number	US-201615058818-A
Country	US
Kind code	A1
Filing date	Mar 2, 2016
Priority date	Jan 6, 2016
Publication date	Jul 6, 2017
Grant date	—

Abstract

A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.

First claim

1 . A method comprising:
attaching a first-level device die to a dummy die; encapsulating the first-level device die in a first encapsulating material; forming first through-vias over and electrically coupled to the first-level device die; attaching a second-level device die over the first-level device die; encapsulating the first through-vias and the second-level device die in a second encapsulating material; and forming redistribution lines over and electrically coupled to the first through-vias and the second-level device die, with the dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material being parts of a composite wafer.

2 . The method of claim 1 further comprising:
before the attaching the first-level device die, attaching the dummy die to a carrier; and
after the redistribution lines are formed, de-bonding the carrier from the dummy die.

3 . The method of claim 1 , wherein the dummy die is a part of an un-sawed dummy wafer, and the method further comprises:
thinning the un-sawed dummy wafer, with the first-level device die attached to the dummy die in the thinned un-sawed dummy wafer; and sawing the composite wafer into a plurality of packages, with the thinned dummy wafer sawed into a plurality of dummy dies, wherein the plurality of dummy dies comprises the dummy die.

4 . The method of claim 1 , wherein the dummy die is a discrete die, and the method further comprises sawing the composite wafer to form a package comprising the dummy die, wherein edges of the dummy die are spaced apart from respective closest edges of the package.

5 . The method of claim 1 , wherein the dummy die is formed of a homogeneous material.

6 . The method of claim 1 , wherein the dummy die comprises silicon.

7 . The method of claim 1 , wherein the dummy die comprises metal.

8 . The method of claim 1 further comprising:
forming second through-vias over and electrically coupled to the first-level device die and the first through-vias;
attaching a third-level device die over the second-level device die; and
encapsulating the second through-vias and the third-level device die in a third encapsulating material, wherein the redistribution lines are formed over the third encapsulating material.

9 . A method comprising:
attaching a dummy wafer over a carrier, wherein the dummy wafer is free from integrated circuit devices; thinning the dummy wafer; attaching first-level device dies to the thinned dummy wafer; stacking second-level device dies over the first-level device dies; forming through-vias electrically coupled to the first-level device dies; forming redistribution lines over and electrically coupled to the through-vias and the second-level device dies; and performing a die saw to separate the dummy wafer, the first-level device dies, and the second-level device dies into a plurality of packages, with each of the plurality of packages comprising a dummy die in the dummy wafer, one of the first-level device dies, and one of the second-level device dies.

10 . The method of claim 9 further comprising:
encapsulating the first-level device dies in a first encapsulating material;
forming a dielectric layer over the first encapsulating material and the first-level device dies; and
encapsulating the second-level device dies and the through-vias in a second encapsulating material, wherein the second encapsulating material is over the dielectric layer.

11 . The method of claim 9 further comprising:
before the attaching the first-level device dies, attaching the dummy wafer to a carrier, with the thinning performed after the dummy wafer is attached to the carrier; and
after the redistribution lines are formed, de-bonding the carrier from the dummy wafer.

12 . The method of claim 9 , wherein the dummy wafer is formed of a homogeneous material.

13 . The method of claim 9 , wherein the dummy wafer comprises silicon.

14 . The method of claim 9 , wherein the dummy wafer comprises metal.

15 . The method of claim 9 , wherein the dummy wafer is free from conductive traces.

16 .- 20 . (canceled)

21 . A method comprising:
attaching a dummy wafer over a carrier; thinning the dummy wafer; attaching a first first-level device die and a second first-level device die to the thinned dummy wafer; encapsulating the first and the second first-level device dies in a first encapsulating material; stacking a second-level device die over the first and the second first-level device dies, wherein the second-level device die overlaps a first portion of each of the first and the second first-level device dies; forming first through-vias overlapping a second portion of each of the first and the second first-level device dies; encapsulating the second-level device die and the first through-vias in a second encapsulating material; stacking a third-level device die over the second-level device die, wherein the third-level device die overlaps a portion of the second-level device die; forming second through-vias overlapping a portion of the second-level device die; encapsulating the third-level device die and the second through-vias in a second encapsulating material; and forming redistribution lines over and electrically coupled to the second through-vias and the third-level device die.

22 . The method of claim 21 , wherein the dummy wafer is formed of a homogenous material.

23 . The method of claim 21 , wherein the first and the second first-level device dies are attached to the dummy wafer through adhesive films.

24 . The method of claim 21 , wherein the dummy wafer is free from conductive traces.

25 . The method of claim 21 further comprising de-bonding the carrier from the dummy wafer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Su An-Jhih
• Chen Wei-Yu
• Chen Ying-Ju
• Lin Tsung-Shu
• Chang Chin-Chuan
• Chen Hsien-Wei
• Wu Wei-Cheng
• Yeh Der-Chyang
• Huang Li-Hsien
• Wu Chi-Hsi

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W72/9413

  on encapsulations · CPC title