Extra gate device for nanosheet

Patent metadata

Field	Value
Publication number	US-2017194216-A1
Application number	US-201615244607-A
Country	US
Kind code	A1
Filing date	Aug 23, 2016
Priority date	Dec 30, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

A method for forming semiconductor devices includes forming a highly doped region. A stack of alternating layers is formed on the substrate. The stack is patterned to form nanosheet structures. A dummy gate structure is formed over and between the nanosheet structures. An interlevel dielectric layer is formed. The dummy gate structures are removed. SG regions are blocked, and top sheets are removed from the nanosheet structures along the dummy gate trench. A bottommost sheet is released and forms a channel for a field effect transistor device by etching away the highly doped region under the nanosheet structure and layers in contact with the bottommost sheet. A gate structure is formed in and over the dummy gate trench wherein the bottommost sheet forms a device channel for the EG device.

First claim

What is claimed and desired protected by Letters Patent is set forth in the appended claims:

1 . A method for forming semiconductor devices, comprising:
patterning a stack of alternating layers formed on a substrate over single gate (SG) regions and extra gate (EG) regions to form nanosheet structures; forming a dummy gate trench over and between the nanosheet structures within an interlevel dielectric formed over the nanosheet structures; removing top sheets of the alternating layers from the nanosheet structures along the dummy gate trench in the EG regions; releasing at least one bottommost sheet of the alternating layers including a semiconductor layer to form a channel for a field effect transistor device by etching away a highly doped region under the nanosheet structures and adjacent layers of the alternating layers in contact with the at least one bottommost sheet; and forming a gate structure in and over the dummy gate trench wherein the at least one bottommost sheet forms a device channel for the EG device.

2 . The method as recited in claim 1 , further comprising doping a surface of the substrate in exposed areas where the extra gate (EG) devices are formed to form the highly doped region.

3 . The method as recited in claim 1 , wherein forming the dummy gate trench further comprises:
forming a dummy gate structure over and between the nanosheet structures; forming the interlevel dielectric layer over the dummy gate structure and the nanosheet structures; and removing dummy gate structures to form the dummy gate trench.

4 . The method as recited in claim 1 , further comprising blocking the SG regions to protect the nanosheet structures in the SG regions.

5 . The method as recited in claim 1 , wherein forming the gate structure includes:
depositing a first dielectric layer; blocking one of the SG regions and the EG regions; and adjusting a thickness of the first dielectric layer of the other of the SG regions and the EG regions that is unblocked.

6 . The method as recited in claim 1 , wherein the nanosheet structures are formed over N wells and P wells to form P-type and N-type devices for SG devices and EG devices.

7 . The method as recited in claim 1 , wherein the nanosheet structures are formed by epitaxially growing alternating layers of the Si and SiGe.

8 . The method as recited in claim 1 , wherein the SG devices include thinner gate dielectric than EG devices.

9 . The method as recited in claim 1 , wherein forming the gate structure includes forming an oxide on the at least one bottommost sheet and depositing a gate dielectric layer on the oxide.

10 . The method as recited in claim 9 , further comprising forming a gate conductor in the gate structure.

11 . The method as recited in claim 1 , wherein the stack of alternating layers includes at least three semiconductor layers and the at least one bottommost layer includes a third semiconductor layer.

Assignees

• IBM

Inventors

• Doris Bruce B
• Hook Terence B
• Wang Junli

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• Y10S977/938

  Field effect transistors, FETS, with nanowire- or nanotube-channel region · CPC title

• H01L21/823857 Primary

  Electricity · mapped topic