Semiconductor device and semiconductor die
US-2024387542-A1 · Nov 21, 2024 · US
Replacement metal gate transistor with controlled threshold voltage
US9190409B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9190409-B2 |
| Application number | US-201414187745-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 24, 2014 |
| Priority date | Feb 25, 2013 |
| Publication date | Nov 17, 2015 |
| Grant date | Nov 17, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A method and structure for a semiconductor device includes a semiconductor substrate and an N-channel transistor and a P-channel transistor provided on the semiconductor substrate. Each of the N-channel transistor and the P-channel transistor has a gate dielectric film on the semiconductor substrate, and a gate electrode is formed on the gate dielectric. The gate electrode comprises a metal conductive layer. The oxygen concentration in the metal conductive layer for the N-channel transistor is different from that for the P-channel transistor.
First claim
Opening claim text (preview).
Having thus described my invention, what I claim as new and desire to secure by Letters Patent is as follows: 1. A semiconductor device, comprising: a semiconductor substrate; and an N-channel transistor and a P-channel transistor provided on the semiconductor substrate, each of the N-channel transistor and the P-channel transistor respectively having a gate dielectric film on said semiconductor substrate, and a gate electrode respectively formed on said gate dielectric, wher…
Assignees
Inventors
Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D84/856Primary
Electricity · mapped topic
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9190409B2 cover?
- A method and structure for a semiconductor device includes a semiconductor substrate and an N-channel transistor and a P-channel transistor provided on the semiconductor substrate. Each of the N-channel transistor and the P-channel transistor has a gate dielectric film on the semiconductor substrate, and a gate electrode is formed on the gate dielectric. The gate electrode comprises a metal con…
- Who is the assignee on this patent?
- Renesas Electronics Corp, IBM
- What technology area does this patent fall under?
- Primary CPC classification H10D84/856. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 17 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).