System for reducing peak electromagnetic interference in a network device

Patent metadata

Field	Value
Publication number	US-2017102731-A1
Application number	US-201514878887-A
Country	US
Kind code	A1
Filing date	Oct 8, 2015
Priority date	Oct 8, 2015
Publication date	Apr 13, 2017
Grant date	—

Abstract

A system for reducing peak electromagnetic interference in a network device. The network device includes multiple clock sources and multiple clocked components. Each clocked component receives a clock signal with an actual clock frequency from a separate clock source. The clock signals have an identical nominal frequency. The actual frequency of each clock signal deviates from the nominal frequency within a predetermined range.

First claim

1 . A network device comprising:
a plurality of clock sources; and a plurality of clocked components, wherein a first clocked component of the plurality of clocked components receives a first clock signal with a first actual clock frequency from a first clock source of the plurality of clock sources, wherein a second clocked component of the plurality of clocked components receives a second clock signal with a second actual clock frequency from a second clock source of the plurality of clock sources, wherein the first actual clock frequency is selected to deviate from a nominal frequency by a first specified amount, within a predetermined range, and wherein the second actual clock frequency is selected to deviate from the nominal frequency by a second specified amount, within the predetermined range.

2 . The network device according to claim 1 , wherein the predetermined range is within the nominal clock frequency+/−100 ppm.

3 . The network device according to claim 1 , wherein the first clock source of the plurality of clock sources is a first crystal oscillator and the second clock source of the plurality of clock sources is a second crystal oscillator.

4 . The network device according to claim 1 , wherein at least one of the plurality of clocked components is one selected from a group consisting of a switch chip, a fabric chip, and a PHY chip in the network device.

5 . The network device of claim 1 , wherein the network device is at least one selected from a group consisting of a switch, a router and a multilayer switch.

6 . The network device of claim 1 , wherein at least one of the clocked components is located on a printed circuit board (PCB) in the network device.

7 . A network device comprising:
a plurality of clock sources; and a component comprising a plurality of clocked subcomponents, wherein a first clocked subcomponent of the plurality of clocked subcomponents receives a first clock signal with a first actual clock frequency from a first clock source of the plurality of clock sources, wherein a second clocked subcomponent of the plurality of clocked subcomponents receives a second clock signal with a second actual clock frequency from a second clock source of the plurality of clock sources, wherein the first actual clock frequency is selected to deviate from a nominal frequency by a first specified amount, within a predetermined range, and wherein the second actual clock frequency is selected to deviate from the nominal frequency by a second specified amount, within the predetermined range.

8 . The network device according to claim 7 , wherein the predetermined range is within the nominal clock frequency+/−100 ppm.

9 . The network device according to claim 7 , wherein the first clock source of the plurality of clock sources is a first crystal oscillator and the second clock source of the plurality of clock sources is a second crystal oscillator.

10 . The network device according to claim 7 , wherein the component is one selected from a group consisting of a switch chip, a fabric chip, and a PHY chip in the network device.

11 . The network device of claim 7 , wherein the network device is at least one selected from a group consisting of a switch, a router and a multilayer switch.

12 . The network device of claim 7 , wherein the component is located on a printed circuit board (PCB) in the network device.

13 . A network device, comprising:
a clock generator that generates a plurality of output clock signals,
wherein each output clock signal of the plurality of output clock signals has a unique clock frequency,
wherein the clock frequencies of the plurality of output clock signals are distributed within a pre-determined frequency range; and
a plurality of clocked components, wherein each clocked component of the plurality of clocked components receives one of the output clock signals.

14 . The network device of claim 13 , wherein one of the output clock signals is a clock signal with a target clock frequency.

15 . The network device of claim 13 , wherein the clock frequencies of the plurality of output clock signals are distributed above and below the target clock frequency.

16 . The network device of claim 13 , wherein the clock generator comprises at least one clock multiplier and wherein at least one of the plurality of output clock signals is generated using the at least one clock multiplier.

17 . The network device of claim 13 , wherein the clock generator comprises at least one clock divider and wherein at least one of the plurality of output clock signals is generated using the at least one clock divider.

18 . The network device according to claim 13 , wherein at least one of the clocked components is one selected from a group consisting of a switch chip, a fabric chip, and a PHY chip in the network device.

19 . The network device of claim 13 , wherein the clock frequencies of the plurality of output clock signals are evenly distributed within the pre-determined frequency range.

20 . The network device of claim 13 , wherein the clock frequencies of the plurality of output clock signals are non-evenly distributed within the pre-determined frequency range.

21 . The network device of claim 13 , wherein the pre-determined frequency range spans 25 ppm.

22 . A network device, comprising:
a clock source that generates a reference clock signal with a reference clock frequency; a clock generator that generates a plurality of derived clock signals from the reference clock signal,
wherein each derived clock signal of the plurality of derived clock signals has a unique clock frequency,
wherein the clock frequencies of the plurality of derived clock signals are distributed within a pre-determined frequency range; and
a clocked component comprising a plurality of clocked subcomponents, wherein each clocked subcomponent of the plurality of clocked subcomponents receives one of the derived clock signals.

Assignees

• Arista Networks Inc

Inventors

• Weaver James
• Hirschman Jeffrey

Classifications

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title