Wafer reinforcement to reduce wafer curvature

Patent metadata

Field	Value
Publication number	US-2017098616-A1
Application number	US-201514873420-A
Country	US
Kind code	A1
Filing date	Oct 2, 2015
Priority date	Oct 2, 2015
Publication date	Apr 6, 2017
Grant date	—

Abstract

A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure.

First claim

1 .- 8 . (canceled)

9 . A method of fabricating a semiconductor chip upon a wafer comprising:
simultaneously forming a deep trench and dual reinforcing trenches, the deep trench and dual reinforcing trenches extending through a silicon on insulator (SOI) layer formed upon a buried insulating layer, through the buried insulating layer formed upon a substrate, and partially through the substrate; filling the deep trench and partially filling the dual reinforcing trenches with a trench material; subsequently filling the partially filled dual reinforcement trenches with reinforcing material.

10 . The method of claim 9 , wherein the reinforcing material differs from the trench material.

11 . The method of claim 10 , wherein the reinforcing material has a material strength measurement greater than the trench material.

12 . The method of claim 9 , wherein each dual reinforcement trench width is greater than the deep trench width.

13 . The method of claim 9 , wherein each dual reinforcement trench depth is greater than the deep trench depth.

14 . The method of claim 9 , wherein the filled dual reinforcement trenches are included in a global reinforcement trench array throughout the wafer.

15 . The method of claim 9 , wherein the filled dual reinforcement trenches are included in a perimeter region at the edge of the wafer.

16 . The method of claim 9 , wherein the filled dual reinforcement trenches are included the wafer kerf.

17 . A method of fabricating a semiconductor structure comprising:
forming a buried insulator upon a wafer substrate; forming an silicon on insulator (SOI) layer upon the buried insulator; forming a mask upon the SOI layer; opening the mask to define locations of a deep trench and to define locations of dual reinforcing trenches; simultaneously forming the deep trench and dual reinforcing trenches by removing the SOI layer, the buried insulating layer, portions of the substrate underlying openings in the mask; filling the deep trench and partially filling the dual reinforcing trenches with trench material, and; subsequently filling the partially filled dual reinforcing trenches with reinforcing material, the filled dual reinforcing trenches opposes transverse loading, axial loading, and torsional loading of the semiconductor structure.

18 . The method of claim 17 , further comprising:
planarizing the filled deep trench and the filled dual reinforcing trenches with the SOI layer top surface removing the mask.

19 . The method of claim 18 , further comprising:
forming a fin by removing portions of the SOI layer exposing the buried insulator thereunder; forming a gate upon the exposed buried insulator and upon the fin covering the fin, the portions of the fin extending outwardly from the gate forming a source and a drain of a fin field effect transistor (FinFET).

20 . The method of claim 19 , further comprising:
forming an interlayer dielectric (ILD) upon exposed upper surfaces of the semiconductor structure covering the gate, and; forming a plurality of contacts within the ILD, a first contact associated with the deep trench, and a second contact associated with at least one of the dual reinforcing trenches.

Assignees

• IBM

Inventors

• Kaltalioglu Erdem
• Kim Andrew T
• Pei Chengwen
• Wang Ping-Chuan

Classifications

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title