Pulse-drive resonant clock with on-the-fly mode change

Patent metadata

Field	Value
Publication number	US-2017031384-A1
Application number	US-201514828898-A
Country	US
Kind code	A1
Filing date	Aug 18, 2015
Priority date	Jul 31, 2015
Publication date	Feb 2, 2017
Grant date	—

Abstract

A pulse-drive resonant clock with on-the fly mode changing provides robust operation in a resonant clock distribution network, in particular for processor circuits having a dynamically-varied operating frequency. The clock drivers for the resonant clock distribution network include a pulse width control circuit having selectable operating modes corresponding to multiple clocking modes of the resonant clock distribution network. The pulse width control circuit includes a delay line that has a selectable delay length to provide pulse enable signals that control the pulse widths of the clock drivers in a sector of the resonant clock distribution network. The delay line responds to a mode control signal so that at least one pulse width of the output is changed from a first pulse width to a second pulse width without generating half-cycles with a pulse width narrower than the first or second pulse width.

First claim

1 . A method of driving a resonant clock distribution network, the method comprising:
driving a drive point of a sector of the resonant clock distribution network with an output of at least one clock driver output stage that receives a clock input from a global clock signal; first enabling and disabling a pull-up driver of the at least one clock driver output stage in response to a first enable input; second enabling and disabling a pull-down driver of the at least one clock driver output stage in response to a second enable input; delaying the global clock signal with a delay line having a selectable delay selected in conformity with a mode select input to produce a delayed global clock signal; and controlling a clock pulse width of the clock driver output stage in conformity with the delayed global clock signal by controlling the first and second enable inputs of the at least one clock driver output by enabling the at least one clock driver output stage in response to changes in state of global clock signal and disabling the at least one clock driver output stage when the changes in state of the global clock signal have propagated through the delay line, and wherein a mode select control logic of the delay line, responsive to the mode select input, prevents the clock pulse width from enabling the at least one clock driver output stage for a duration shorter than a delay time of the delay line when the mode select input changes state.

2 - 3 . (canceled)

4 . The method of claim 1 , wherein the delaying is performed by a tapped delay line, and wherein the mode select control logic, in conformity with the mode select input, delays a selection change of the tapped delay line until a predetermined time after a last transition of the global clock signal has occurred.

5 . The method of claim 4 , wherein the mode select control logic delays the selection change of the tapped delay line by latching the mode select input with a delayed version of the global clock signal.

6 . The method of claim 1 , wherein the delaying is performed by a pair of tapped delay lines that individually delay the global clock signal to perform a corresponding one of the first and second enabling and disabling.

7 . The method of claim 6 , wherein the mode select control logic delays the selection change of a first one of the tapped delay lines by latching the mode select input with a first delayed version of the global clock signal and delays the selection change of a second one of the tapped delay lines by lathing the mode select input with a second delayed version of the global clock signal.

8 . A method of driving a resonant clock distribution network, the method comprising:
driving a drive point of a sector of the resonant clock distribution network with an output of at least one clock driver output stage that receives a clock input from a global clock signal; first enabling and disabling a pull-up driver of the at least one clock driver output stage in response to a first enable input; second enabling and disabling a pull-down driver of the at least one clock driver output stage in response to a second enable input; delaying the global clock signal with a delay line having a selectable delay selected in conformity with a mode select input to produce a delayed global clock signal, wherein the delaying is performed by a cascade of delay elements having a selectable drive strength that is selected in response to the mode select input, whereby the delay of the delay line is adjusted without causing a transient at the output of the delay line; controlling a clock pulse width of the clock driver output stage in conformity with the delayed global clock signal by controlling the first and second enable inputs of the at least one clock driver output by enabling the at least one clock driver output stage in response to changes in state of global clock signal and disabling the at least one clock driver output stage when the changes in state of the global clock signal have propagated through the delay line.

9 . The method of claim 8 , wherein the selectable drive strength is provided by at least some of the delay elements having pull-up and pull-down devices connected by a selectable pass current or impedance to corresponding power supply rail.

Assignees

• IBM

Inventors

• Bucelot Thomas J
• Franch Robert L
• Restle Phillip J
• Shan David Wen-Hao
• Vezyrtzis Christos

Classifications

• H03K5/159

  Applications of delay lines not covered by the preceding subgroups · CPC title

• H03K7/08

  Duration or width modulation {; Duty cycle modulation} · CPC title

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title