Memory management within secure migratable architecture

Patent metadata

Field	Value
Publication number	US-2017024129-A1
Application number	US-201615048172-A
Country	US
Kind code	A1
Filing date	Feb 19, 2016
Priority date	Jun 30, 2014
Publication date	Jan 26, 2017
Grant date	—

Abstract

Methods and systems for executing virtualized processes on a computing system are disclosed, including techniques for memory management when executing such processes. One method includes allocating a portion of memory to a process hosted by an operating system of a computing system having a first computing architecture, the process comprising a firmware environment implementing a second computing architecture different from the first computing architecture, the first computing architecture applying virtual addressing to the portion of memory. The method further includes receiving a memory access request within the process, the memory access request including a direct address of a memory location within the portion of memory, according to the second computing architecture, and passing to the operating system the memory access request from the process.

First claim

1 . A computing system comprising:
a programmable circuit configured to execute instructions according to a first computing architecture; a memory communicatively connected to the programmable circuit, the memory storing software executable by the programmable circuit, the software including:
an operating system, wherein the operating system and first computing architecture uses virtual addressing to address the memory; and
a process including a firmware environment representing a virtual computing system having a second computing architecture different from the first computing architecture and one or more workloads to be executed within the process, wherein:
upon instantiation of the process, the operating system allocates a portion of the memory for use by the process; and
within the firmware environment, the second computing architecture directly addresses the portion of the memory for use by the process.

2 . The system of claim 1 , wherein, in the first architecture, each memory address has a first length and in the second architecture each memory address within the portion of memory has a second length, wherein the second length is greater than the first length.

3 . The system of claim 2 , wherein the second length comprises a 64 bit value.

4 . The system of claim 3 , wherein the first length comprises a 48 bit virtual address.

5 . The system of claim 1 , wherein the programmable circuit and operating system provide paging in association with the portion of the memory for use by the process in a manner obscured to the one or more workloads.

6 . The system of claim 1 , wherein the first computing architecture defines a first length for an integer data type, and the second computing architecture defines a second length for an integer data type different from the first length.

7 . The system of claim 6 , wherein the second length is greater than the first length and an integer multiple of the first length.

8 . The system of claim 1 , wherein the portion of the memory includes at least a first memory segment associated with a first tag segment, the first tag segment including tags that are associated with each of the memory locations within the first memory segment.

9 . The system of claim 8 , wherein each tag of the tags included in the first tag segment is assigned a value selected from among a plurality of values.

10 . The system of claim 9 , wherein the plurality of values including unassigned values configurable for future use.

11 . The system of claim 8 , wherein the first memory segment is associated with a first memory descriptor stored in a memory descriptor collection, the first memory descriptor including a location of the first memory segment and a location of the first tag segment.

12 . A method of executing a virtualized process on a computing system, the method comprising:
allocating a portion of memory to a process hosted by an operating system of a computing system having a first computing architecture, the process comprising a firmware environment implementing a second computing architecture different from the first computing architecture, the first computing architecture applying virtual addressing to the portion of memory; receiving a memory access request within the process, the memory access request including a direct address of a memory location within the portion of memory, according to the second computing architecture; and passing to the operating system the memory access request from the process.

13 . The method of claim 12 , wherein the operating system translates the direct address to a virtual address within the first computing architecture to the memory location.

14 . The method of claim 12 , further comprising performing a paging process by the operating system and a native processor of the computing system to access the portion of memory.

15 . A computer-readable storage medium comprising computer-executable instructions stored thereon which, when executed by a computing system, cause the computing system to perform a method comprising:
allocating a portion of memory to a process hosted by an operating system of a computing system having a first computing architecture, the process comprising a firmware environment implementing a second computing architecture different from the first computing architecture, the first computing architecture applying virtual addressing to the portion of memory; receiving a memory access request within the process, the memory access request including a direct address of a memory location within the portion of memory, according to the second computing architecture; and passing to the operating system the memory access request from the process.

Assignees

• Beale Andrew Ward
• Strong David
• Unisys Corp

Inventors

• Beale Andrew Ward
• Strong David

Classifications

• G06F3/0664

  at device level, e.g. emulation of a storage device or system · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F2009/45583

  Memory management, e.g. access or allocation · CPC title