Synchronizing a translation lookaside buffer with an extended paging table

Patent metadata

Field	Value
Publication number	US-2016019165-A1
Application number	US-201514867024-A
Country	US
Kind code	A1
Filing date	Sep 28, 2015
Priority date	Aug 15, 2006
Publication date	Jan 21, 2016
Grant date	—

Abstract

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

First claim

What is claimed is:

1 . A multi-core processor comprising:
a first register to reference a set of page tables, the set of page tables to provide a mapping of guest virtual addresses to guest physical addresses; a second register to reference an active set of extended page tables, including one of:
a first set of extended page tables to provide a mapping of guest physical addresses to host physical addresses for a first virtual machine, the first set of extended page tables to reference a portion of host physical address space associated with the first virtual machine, and
a second set of extended page tables to provide a mapping of guest physical addresses to host physical addresses for a second virtual machine, the second set of extended page tables to reference a portion of host physical address space associated with the second virtual machine;
address translation logic to access the set of page tables and the set of extended page tables to translate a guest virtual address to a guest physical address and to translate the guest physical address to a host physical address in response to a memory access request including the guest virtual address; a translation look-aside buffer (TLB) to cache a plurality TLB entries, including guest physical address to host physical address translations; and execution logic, in response to a TLB invalidate instruction, to invalidate only TLB entries associated with the first virtual machine, independent of corresponding guest physical addresses.

2 . The multi-core processor of claim 1 , further comprising access logic to enable use of the set of extended page tables.

3 . The multi-core processor of claim 2 , wherein use of the set of extended page tables is based on an EPT enable indicator.

4 . The multi-core processor of claim 1 , wherein the TLB is to cache virtual address to guest physical address translations.

5 . A system comprising:
a flash memory to store instructions and data for performing program execution; a random access memory; and a multi-core processor coupled to the flash memory and the random access memory, the multi-core processor comprising:
a first register to reference a set of page tables, the set of page tables to provide a mapping of guest virtual addresses to guest physical addresses;
a second register to reference an active set of extended page tables, including one of:
a first set of extended page tables to provide a mapping of guest physical addresses to host physical addresses for a first virtual machine, the first set of extended page tables to reference a portion of host physical address space associated with the first virtual machine, and
a second set of extended page tables to provide a mapping of guest physical addresses to host physical addresses for a second virtual machine, the second set of extended page tables to reference a portion of host physical address space associated with the second virtual machine;

address translation logic to access the set of page tables and the set of
extended page tables to translate a guest virtual address to a guest physical address and to translate the guest physical address to a host physical address in response to a memory access request including the guest virtual address; a translation look-aside buffer (TLB) to cache a plurality TLB entries, including guest physical address to host physical address translations; and execution logic, in response to a TLB invalidate instruction, to invalidate only TLB entries associated with the first virtual machine, independent of corresponding guest physical addresses.

6 . The system of claim 5 , further comprising access logic to enable use of the set of extended page tables.

7 . The system of claim 6 , wherein use of the set of extended page tables is based on an EPT enable indicator.

8 . The system of claim 5 , wherein the TLB is to cache virtual address to guest physical address translations.

9 . The system of claim 5 , wherein the system is a server.

Assignees

• Intel Corp

Inventors

• Bennett Steven M
• Anderson Andrew V
• Neiger Gilbert
• Uhlig Richard A
• Rodgers Scott Dion
• Sankaran Rajesh M
• Rust Camron
• Schoenberg Sebastian

Classifications

• G06F12/1036

  for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) · CPC title

• G06F2212/50

  Control mechanisms for virtual memory, cache or TLB · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F12/1054 Primary

  the data cache being concurrently physically addressed · CPC title

• G06F2212/657

  Virtual address space management · CPC title