Secure migratable architecture having high availability

Patent metadata

Field	Value
Publication number	US-2016371101-A1
Application number	US-201615048154-A
Country	US
Kind code	A1
Filing date	Feb 19, 2016
Priority date	Jun 30, 2014
Publication date	Dec 22, 2016
Grant date	—

Abstract

Systems and methods are disclosed that ensure high availability of such an architecture hosted on commodity platforms. One method includes initializing, by an operating system, execution of a process by the programmable circuit, the process including a firmware environment representing a virtual computing system having a second computing architecture different from a first computing architecture of a computing system on which the operating system and process reside, the process further including one or more workloads to be executed within the process. The method also includes allocating a portion of the memory for use by the process, the portion of memory including a plurality of memory segments, and generating a plurality of area descriptors associated with the plurality of memory segments, each of the area descriptors defining a location and length of a corresponding memory segment. The method includes quiescing execution of the process and capturing contents of the portion of memory and the plurality of area descriptors associated with the process.

First claim

1 . A system comprising:
a computing system including:
a programmable circuit configured to execute instructions according to a first computing architecture;
a memory communicatively connected to the programmable circuit, the memory storing software executable by the programmable circuit, the software including:
a first process including a firmware environment representing a virtual computing system having a second computing architecture different from the first computing architecture and one or more workloads to be executed within the process,

the software executable to perform a method including:
initializing, by an operating system, execution of the first process by the programmable circuit;
allocating a portion of the memory for use by the first process, the portion of memory including a plurality of memory segments;
generating a plurality of area descriptors associated with the plurality of memory segments, each of the area descriptors defining a location and length of a corresponding memory segment;
quiescing execution of the first process;
capturing contents of the portion of memory and the plurality of area descriptors associated with the first process; and
transferring a binary including the first process and the state of the portion of memory associated with the first process to a second location.

2 . The system of claim 1 , wherein the method performed by the software further includes:
at the second location, unpacking the portion of memory into a second portion of memory and updating the area descriptors to reference the second portion of memory; installing the first process at the second location from the binary; and continuing operation of the first process at the second location.

3 . The system of claim 2 , wherein the second location comprises a second computing system communicatively connected to the first computing system.

4 . The system of claim 1 , wherein the second location comprises a second memory location within the computing system.

5 . The system of claim 1 , wherein the software is further executable to perform releasing the portion of the memory allocated to the first process.

6 . The system of claim 1 , wherein, during execution of the first process on the computing system, the portion of memory is replicated on the second computing system.

7 . The system of claim 6 , wherein quiescing execution of the first process and initializing execution of the second process occur without restarting the computing system.

8 . The system of claim 1 , wherein the first process includes one or more call-outs useable by the one or more workloads to directly execute instructions within the first computing architecture.

9 . The system of claim 1 , wherein the software is configured to, prior to initializing execution of the process by the programmable circuit, enumerate a specific version level of the firmware environment operating within the process.

10 . The system of claim 1 , wherein the software is further configured to replace the firmware with updated firmware while the first process is queisced.

11 . A computer-implemented method comprising:
initializing, by an operating system, execution of a process by the programmable circuit, the process including a firmware environment representing a virtual computing system having a second computing architecture different from a first computing architecture of a computing system on which the operating system and process reside, the process further including one or more workloads to be executed within the process; allocating a portion of the memory for use by the process, the portion of memory including a plurality of memory segments; generating a plurality of area descriptors associated with the plurality of memory segments, each of the area descriptors defining a location and length of a corresponding memory segment; quiescing execution of the process; and capturing contents of the portion of memory and the plurality of area descriptors associated with the process.

12 . The method of claim 11 , further comprising replacing the firmware with updated firmware while the first process is queisced.

13 . The method of claim 11 , further comprising transferring a binary including the process and the state of the portion of memory associated with the process to a second location.

14 . The method of claim 13 , further comprising:
at the second location, unpacking the portion of memory into a second portion of memory and updating the area descriptors to reference the second portion of memory; installing the process at the second location from the binary; and continuing operation of the process at the second location.

15 . The method of claim 13 , further comprising deallocating the portion of memory.

16 . The method of claim 13 , wherein the portion of memory is located on a first computing system and the second portion of memory is located on a second computing system, and wherein deallocating the portion of memory frees memory resources of the first computing system.

17 . The method of claim 11 , further comprising, during operation of the process, requesting allocation by the operating system of one or more processing cores available on the computing system.

18 . The method of claim 11 , further comprising, during operation of the process, requesting allocation by the operating system of one or more additional memory segments available on the computing system.

19 . The method of claim 11 , further comprising enumerating a specific version level of the firmware environment operating within the process.

20 . A computer-readable storage medium comprising computer-executable instructions stored thereon which, when executed by a computing system, cause the computing system to perform a method comprising:
initializing, by an operating system, execution of a process by the programmable circuit, the process including a firmware environment representing a virtual computing system having a second computing architecture different from a first computing architecture of a computing system on which the operating system and process reside, the process further including one or more workloads to be executed within the process; allocating a portion of the memory for use by the process, the portion of memory including a plurality of memory segments; generating a plurality of area descriptors associated with the plurality of memory segments, each of the area descriptors defining a location and length of a corresponding memory segment; quiescing execution of the process; capturing contents of the portion of memory and the plurality of area descriptors associated with the process; and transferring a binary including the process and the state of the portion of memory associated with the process to a second location.

Assignees

• Beale Andrew Ward
• Strong David
• Unisys Corp

Inventors

• Beale Andrew Ward
• Strong David

Classifications

• G06F9/455 Primary

  Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines · CPC title

• G06F9/5016

  the resource being the memory · CPC title

• G06F8/65

  Updates (security arrangements therefor G06F21/57) · CPC title

• H04L63/20 Primary

  for managing network security; network security policies in general (filtering policies H04L63/0227) · CPC title

• G06F2212/1004

  Compatibility, e.g. with legacy hardware · CPC title