Transistor using piezoresistor as channel, and electronic circuit

Patent metadata

Field	Value
Publication number	US-2017005265-A1
Application number	US-201515125840-A
Country	US
Kind code	A1
Filing date	Mar 6, 2015
Priority date	Mar 14, 2014
Publication date	Jan 5, 2017
Grant date	—

Abstract

A transistor includes: a piezoresistor through which carriers conduct; a source that injects the carriers into the piezoresistor; a drain that receives the carriers from the piezoresistor; a piezoelectric material that is located so as to surround the piezoresistor and applies a pressure to the piezoresistor; and a gate that applies a voltage to the piezoelectric material so that the piezoelectric material applies a pressure to the piezoresistor.

First claim

1 . A transistor characterized by comprising:
a piezoresistor through which carriers conduct; a source that injects the carriers into the piezoresistor; a drain that receives the carriers from the piezoresistor; a piezoelectric material that is located so as to surround the piezoresistor and applies a pressure to the piezoresistor; and a gate that applies a voltage to the piezoelectric material so that the piezoelectric material applies a pressure to the piezoresistor.

2 . The transistor of claim 1 , wherein
the gate is located so as to surround the piezoelectric material, and the piezoelectric material is dielectrically polarized in a direction from the piezoresistor to the gate or in a direction from the gate to the piezoresistor.

3 . The transistor of claim 1 , wherein
a plurality of the gates are located in a direction parallel to a conduction direction of the carriers conducting through a channel in the piezoresistor, and the piezoelectric material is dielectrically polarized in the direction parallel to the conduction direction.

4 . The transistor of claim 1 , wherein
the piezoelectric material is located so as to surround the piezoresistor in all directions perpendicular to a conduction direction of the carriers.

5 . The transistor of claim 1 , wherein
the piezoelectric material is located so as to partially surround the piezoresistor in directions perpendicular to a conduction direction of the carriers.

6 . The transistor of claim 1 , further comprising:
a support that is formed on a substrate and supports the piezoresistor, wherein an upper surface of the piezoresistor is curved, and the piezoelectric material surrounds the upper surface of the piezoresistor and a side surface of the support.

7 . The transistor of claim 6 , wherein
a height of the support is greater than a width of the piezoresistor.

8 . The transistor of claim 6 , wherein
a material of the support is identical to a material of the piezoresistor.

9 . The transistor of claim 6 , wherein
a material of the support differs from a material of the piezoresistor.

10 . A transistor comprising:
a piezoresistor through which carriers conduct in a first direction; a source that injects the carriers into the piezoresistor; a drain that receives the carriers from the piezoresistor; a piezoelectric material that applies a pressure to the piezoresistor in a second direction intersecting with the first direction; and a gate that applies a voltage to the piezoelectric material so that the piezoelectric material applies a pressure to the piezoresistor.

11 . The transistor of claim 1 , wherein
the source and the drain are symmetrical to each other across an intermediate plane between the source and the drain in the piezoresistor, and each of the piezoresistor, the piezoelectric material, and the gate is symmetric with respect to the intermediate plane.

12 . An electronic circuit comprising:
a circuit that is connected between a first power source and a second power source; and the transistor of claim 1 in which one of the source and the drain is coupled to the first power source, another of the source and the drain is coupled to a supply terminal of the circuit, and a signal that cuts electric power supplied to the circuit is input to the gate.

13 . The electronic circuit of claim 12 , further comprising:
a bistable circuit that stores data; and a non-volatile element that stores, in a non-volatile manner, data stored in the bistable circuit, and restores, to the bistable circuit, the data stored in a non-volatile manner, wherein the circuit is the bistable circuit.

14 . The electronic circuit of claim 13 , wherein
the non-volatile element is connected between a node in the bistable circuit and a control line.

15 . An electronic circuit comprising:
a non-volatile memory cell including:
a non-volatile element; and
the transistor of claim 1 in which the source or the drain is connected in series to the non-volatile element.

16 . An electronic circuit comprising:
first and second transistors that are the transistor of claim 1 and complement each other, wherein dielectric polarization directions of the piezoelectric materials of the first and second transistors are opposite to each other, and are directions that allow the piezoelectric material to apply a pressure to the piezoresistor when a positive voltage or a negative voltage with respect to the source is applied to the gate.

17 . An electronic circuit comprising:
a circuit that is connected between a first power source and a second power source; and the transistor of claim 10 in which one of the source and the drain is coupled to the first power source, another of the source and the drain is coupled to a supply terminal of the circuit, and a signal that cuts electric power supplied to the circuit is input to the gate.

18 . The electronic circuit of claim 17 , further comprising:
a bistable circuit that stores data; and a non-volatile element that stores, in a non-volatile manner, data stored in the bistable circuit, and restores, to the bistable circuit, the data stored in a non-volatile manner, wherein the circuit is the bistable circuit.

19 . An electronic circuit comprising:
a non-volatile memory cell including:
a non-volatile element; and
the transistor of claim 10 in which the source or the drain is connected in series to the non-volatile element.

20 . An electronic circuit comprising:
first and second transistors that are the transistor of claim 10 and complement each other,
wherein dielectric polarization directions of the piezoelectric materials of the first and second transistors are opposite to each other, and are directions that allow the piezoelectric material to apply a pressure to the piezoresistor when a positive voltage or a negative voltage with respect to the source is applied to the gate.

Assignees

• Japan Science & Tech Agency

Inventors

• Sugahara Satoshi
• SHUTO Yusuke
• Kurosawa Minoru
• Funakubo Hiroshi
• Yamamoto Shuichiro

Classifications

• H01L27/2436

  Electricity · mapped topic

• H01L49/00 Primary

  Electricity · mapped topic

• H01L27/226

  Electricity · mapped topic

• G11C14/009

  and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material · CPC title

• H03K3/356 Primary

  Bistable circuits · CPC title