Implementing resistance defect performance mitigation using test signature directed self heating and increased voltage

Patent metadata

Field	Value
Publication number	US-2016379898-A1
Application number	US-201514750471-A
Country	US
Kind code	A1
Filing date	Jun 25, 2015
Priority date	Jun 25, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

A method and system are provided for implementing resistive defect performance mitigation for integrated circuits. A test is generated for identifying resistive defects. A first self heating repair process is performed for repairing resistive defects. Testing is performed to identify a mitigated resistive defect and a functional integrated circuit. Responsive to identifying a resistive defect not being mitigated and a functional integrated circuit, a second repair process is performed, then testing is performed again.

First claim

1 - 9 . (canceled)

10 . A computer system for implementing resistive defect performance mitigation for integrated circuits comprising:
a processor; a test generator; a resistive defect performance mitigation control; said processor using said test generator and said resistive defect performance mitigation control to implement resistive defect performance mitigation for a sample integrated circuits; said processor using said test generator for identifying resistive defects; said processor using said resistive defect performance mitigation control for performing a first self heating repair process for repairing resistive defects; said processor using said test generator for performing testing to identify a mitigated resistive defect and a functional integrated circuit; and said processor using said resistive defect performance mitigation control responsive to identifying a resistive defect not being mitigated and a functional integrated circuit, for performing a second repair process, and repeating testing to identify a mitigated resistive defect and a functional integrated circuit.

11 . The system as recited in claim 10 includes control code stored on a computer readable medium, and wherein said processor uses said control code for implementing resistive defect performance mitigation for integrated circuits.

12 . The system as recited in claim 10 wherein the first self heating repair process includes repeatedly switching a signal to a circuit path containing the resistive defect at a selected frequency and a selected voltage for a set duration.

13 . The system as recited in claim 12 wherein said selected frequency is approximately equal or slightly above a maximum frequency at which the integrated circuit functions, and said set duration equals a set number of microseconds allowing millions of switches.

14 . The system as recited in claim 12 wherein the repeated switching is provided at a set elevated voltage to enhance localized heating and stressing of any residual dielectric films in the connecting area.

15 . The system as recited in claim 10 wherein repairing resistive defects includes one or more of repairing resistive connections in a contact, a via, and a high resistance defect present in an internally embedded interconnect.

16 . The system as recited in claim 10 wherein performing testing to identify a mitigated resistive defect and a functional integrated circuit includes said processor using said resistive defect performance mitigation control, applying an appropriate voltage for use of the integrated circuit to a defect node, and testing to identify a mitigated resistive defect and a functional integrated circuit.

17 . The system as recited in claim 10 wherein said second repair process includes said processor using said resistive defect performance mitigation control, using a laser to enhance the local heating.

18 . The system as recited in claim 10 wherein said second repair process includes said processor using said resistive defect performance mitigation control, providing incremental voltage steps to a defect node and repeating until a mitigated resistive defect is identified or a maximum voltage is reached.

19 . The system as recited in claim 10 includes said processor using said resistive defect performance mitigation control, identifying a successful repair, responsive to identifying a resistive defect being mitigated and a functional integrated circuit being identified.

20 . The system as recited in claim 10 includes said processor using said resistive defect performance mitigation control, discarding the integrated circuit, responsive to a functional integrated circuit not being identified.

Assignees

• IBM

Inventors

• Erickson Karl R
• Paone Phil C
• Paulsen David P
• Sheets Ii John E
• Uhlmann Gregory J

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P74/232 Primary

  comprising connection or disconnection of parts of a device in response to a measurement · CPC title

• G05B19/41875

  characterised by quality surveillance of production · CPC title

• G05B2219/40361

  Category of performance criteria · CPC title