Semiconductor device with charge compensation region underneath gate trench

Patent metadata

Field	Value
Publication number	US-9443973-B2
Application number	US-201414554193-A
Country	US
Kind code	B2
Filing date	Nov 26, 2014
Priority date	Nov 26, 2014
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A semiconductor substrate has a main surface and a rear surface vertically spaced apart from the main surface, a first doped region, a second doped region and a third doped region. The third doped region is interposed between the first and second doped regions beneath the main surface. Field plate trenches having field plates vertically extend from the main surface to a bottom that is arranged in the first doped region. A gate trench having a gate electrode vertically extends from the main surface to the first doped region. A compensation zone vertically extends from the bottom of the gate trench deeper into the first doped region. The compensation zone is laterally aligned with the gate trench and is adjacent to the field plates along a cross-sectional plane of the device that is parallel to the main surface.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate comprising a main surface and a rear surface vertically spaced apart from the main surface, a first doped region, a second doped region and a third doped region, the second and third doped regions being formed in the first doped region, the second doped region extending from the main surface into the substrate, the third doped region interposed between the first and second doped regions beneath the main surface;
first and second field plate trenches vertically extending from the main surface to a bottom that is arranged in the first doped region;
first and second field plates arranged in the first and second field plate trenches, respectively, and being dielectrically insulated from the substrate;
a gate trench laterally arranged between the first and second field plate trenches and vertically extending from the main surface through the second and third doped regions so that a bottom of the gate trench is arranged in the first doped region;
a gate electrode arranged in the gate trench and being dielectrically insulated from the substrate, the gate electrode being configured to control an electrically conductive channel in the third doped region; and
a compensation zone vertically extending from the bottom of the gate trench deeper into the first doped region;
third and fourth field plate trenches extending from the main surface to a bottom that is arranged in the first doped region; and
third and fourth field plates arranged in the third and fourth field plate trenches, respectively, and being dielectrically insulated from the substrate,
wherein the compensation zone is laterally aligned with the gate trench along a cross-sectional plane of the device that is orthogonal to the main surface,
wherein the compensation zone is adjacent to the field plates along a cross-sectional plane of the device that is parallel to the main surface,
wherein the first and second doped regions have first conductivity type, and
wherein the third doped region and the compensation zone have a second conductivity type,
wherein the gate electrode is laterally arranged between third and fourth field plate trenches, and
wherein the compensation zone is arranged underneath a portion of the gate trench that is equidistant to the first, second, third and fourth field plates,
wherein the first, second, third and fourth field plate trenches each form a closed loop in a plane parallel to the main surface, wherein the first, second, third and fourth field plate trenches are collectively arranged in a rectangle, the rectangle being formed in the plane parallel to the main surface and being defined by center points of the closed loops, and
wherein the portion of the gate trench that is equidistant to the first, second, third and fourth field plates is at a center of the rectangle,
wherein the gate trench comprises first and second lateral portions that form an intersection with one another at the center of the rectangle, and wherein the compensation zone extends from the bottom of the gate trench at the intersection, and
wherein the compensation zone is interrupted at regions of the substrate in which laterally adjacent ones of the first, second, third and fourth field plate trenches are closest to one another.

2. A semiconductor device of claim 1 , wherein only the gate electrode and a gate dielectric are arranged in the gate trench, and wherein a bottom of the compensation zone is spaced closer to the main surface than the bottoms of the first and second field plate trenches.

3. The semiconductor device of claim 1 , wherein the compensation zone is configured to maximize a blocking-state electric field at a location between the main surface and the bottom of at least one of the field plate trenches and to reduce the blocking-state electric field at the bottom of the same field plate trench, wherein the blocking-state electric field is an electric field that develops in the first doped region when a p-n junction between the first and third doped regions is reverse biased.

4. The semiconductor device of claim 1 , wherein the first and second lateral portions of the gate trench are orthogonal to one another.

5. The semiconductor device of claim 1 , wherein the compensation zone extends from the bottom of the gate trench only at the intersection.

6. The semiconductor device of claim 1 , wherein the first conductivity type is n-type and wherein the second conductivity type is p-type.

7. A power transistor, comprising:
a semiconductor substrate comprising a main surface and a rear surface vertically spaced apart from the main surface, a drift region, a source region, and a body region, the source region and the body region being formed in the drift region, the source region extending from the main surface into the substrate, the body region interposed between the source region and the drift region beneath the main surface;
first and second field plate trenches vertically extending from the main surface to a bottom that is arranged in the drift region;
first and second field plates arranged in the first and second field plate trenches, respectively, and being dielectrically insulated from the substrate;
a gate trench laterally arranged between the first and second field plate trenches and vertically extending from the main surface through the source region and the body region so that the gate trench has a bottom arranged in the drift region;
a gate electrode arranged in the gate trench and being dielectrically insulated from the substrate, the gate electrode being configured to control an electrically conductive channel in the body region; and
a compensation zone vertically extending from the bottom of the gate trench deeper into the drift region,
a drain region extending from the rear surface into the semiconductor substrate and coupled to the drift region;
a source electrode arranged on the main surface and electrically connected to the source region; and
a drain electrode arranged on the rear surface and electrically connected to the drain region,
third and fourth field plate trenches extending from the main surface to a bottom that is arranged in the drift region; and
third and fourth field plates arranged in the third and fourth field plate trenches, respectively, and being dielectrically insulated from the substrate,
wherein the compensation zone is laterally aligned with the gate trench along a cross-sectional plane of the device that is orthogonal to the main surface, and
wherein the compensation zone is adjacent to the field plates along a cross-sectional plane of the device that is parallel to the main surface,
wherein the gate electrode is laterally arranged between third and fourth field plate trenches,
wherein the compensation zone is arranged underneath a portion of the gate trench that is equidistant to the first, second, third and fourth field plates,
wherein the drift region, the source region, and the drain region are n-type regions, the drift region being more lightly doped than the source and drain regions,
wherein the body region and the compensation zone are p-type regions, the compensation zone having a different doping concentration than the body region, and
wherein the compensation zone is interrupted at regions within the drift zone in which laterally adjacent ones of the first, second, third and fourth field plate trenches are closest to one another.

8. The power transistor of claim 7 , wherein the first, second, third and fourth field plate trenches each form a closed loop in a plane parallel to the main surface, wherein the first, second, third and fourth field plate trenches are collectively arranged in a rectangle, the rectangle being formed in

Assignees

• Infineon Technologies Austria Ag

Inventors

• Jin Minghao
• Yip Li Juin
• Blank Oliver
• Vielemeyer Martin
• Hirler Franz

Classifications

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P30/212

  Through-implantation · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title