Semiconductor memory devices and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9287349-B2
Application number	US-201213688840-A
Country	US
Kind code	B2
Filing date	Nov 29, 2012
Priority date	Mar 2, 2012
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

According to example embodiments of inventive concepts, method of forming a semiconductor memory devices includes sequentially forming a first mold layer, a first support layer, a second mold layer, and a second support layer on a substrate, forming lower electrodes penetrating the second support layer, the second mold layer, the first support layer, and the first mold layer on the substrate, patterning the second support layer to form a second support pattern including an opening, removing the second mold layer to expose portions of sidewalls of the lower electrodes, and etching the exposed sidewalls of the lower electrodes.

First claim

What is claimed is:

1. A method of forming a semiconductor memory device, comprising:
sequentially forming a first mold layer, a first support layer, a second mold layer, and a second support layer on a substrate;
forming lower electrodes that penetrate the second support layer, the second mold layer, the first support layer, and the first mold layer on the substrate, each of the lower electrodes including a lower portion in the first mold layer and an upper portion in the second mold layer, a width of the upper portion being greater than a width of the lower portion;
patterning the second support layer to form a second support pattern, the second support pattern including an opening;
removing the second mold layer to expose sidewalls of the upper portions of the lower electrodes, wherein the exposed sidewalls of the upper portions of the lower electrodes are disposed between the second support pattern and the first support layer vertically spaced apart from each other; and
etching the exposed sidewalls of the upper portions of the lower electrodes to increase a distance between the upper portions of the lower electrodes adjacent to each other, after the removing the second mold layer.

2. The method of claim 1 , wherein
the lower electrodes are spaced apart from each other;
each of the lower electrodes vertically penetrates the second support layer, the second mold layer, the first support layer, and the first mold layer, and
the lower electrodes are electrically connected to the substrate.

3. The method of claim 1 , wherein the opening of the second support pattern exposes a portion of the second mold layer before the removing the second mold layer.

4. The method of claim 1 , wherein the removing the second mold layer includes:
wet-etching the second mold layer through the opening of the second support pattern.

5. The method of claim 1 , wherein etching the exposed sidewalls of the portions of the lower electrodes includes:
performing a wet etching process to reduce widths of the exposed portions of the lower electrodes.

6. The method of claim 1 , further comprising:
patterning the first support layer to form a first support pattern,
the first support pattern including an opening that exposes a portion of the first mold layer; and

removing the first mold layer through the opening of the first support pattern.

7. The method of claim 6 , wherein the forming lower electrodes includes:
forming the lower electrodes so a middle portion of the lower electrodes penetrates the first support pattern.

8. The method of claim 1 , further comprising:
forming a capacitor dielectric layer covering surfaces of the lower electrodes on the substrate; and
forming an upper electrode layer on the capacitor dielectric layer.

9. The method of claim 1 , wherein a top surface of the second support pattern is substantially coplanar with top surfaces of the lower electrodes.

10. The method of claim 1 , wherein the forming lower electrodes includes:
forming each of the lower electrodes as a pillar-shape.

11. The method of claim 1 , further comprising:
forming an etch stop layer on the substrate before forming the first mold layer, wherein the forming the lower electrodes includes,
forming through-holes through the second support layer, the second mold layer, the first support layer, the first mold layer, and the etch stop layer, and
forming the lower electrodes in the through-holes so a bottom surface of the etch stop layer is substantially coplanar with bottom surfaces of the lower electrodes.

12. The method of claim 1 , wherein
the first and second mold layers include silicon oxide; and
the first and second support layers include one of silicon nitride and germanium oxide.

13. A method of forming a semiconductor memory device, comprising:
forming a stacked structure on a substrate,
the stacked structure including a plurality of lower electrodes in a plurality of holes defined by a plurality of mold layers and support layers alternately stacked,
the plurality of lower electrodes being spaced apart and each including an upper portion between two of the plurality of support layers and a lower portion, a width of the upper portion being greater than a width of the lower portion;

removing one of the plurality of mold layers to expose sidewalls of the upper portions of the plurality of lower electrodes, wherein the exposed sidewalls of the upper portions of the plurality of lower electrodes are disposed between the two of the plurality of support layers vertically spaced apart from each other; and
etching the exposed sidewalls of the plurality of lower electrodes to increase a distance between the upper portions of the lower electrodes adjacent to each other after the removing one of the plurality of mold layers.

14. The method of claim 13 , wherein the forming the stacked structure includes: forming an etch stop layer, a first mold layer of the plurality of mold layers, a first support layer of the plurality of support layers, a second mold layer of the plurality of mold layers, and a second support layer of the plurality of support layers sequentially stacked on the substrate;
patterning the etch stop layer, the first mold layer, the first support layer, the second mold layer, and the second support layer to form a plurality of openings spaced apart from each other and defined by the etch stop layer, the first mold layer, the first support layer, the second mold layer, and the second support layer, and
forming the lower electrodes in the plurality of openings,
the plurality of openings corresponding to the plurality of holes defined by the plurality of mold layers and support layers alternately stacked.

15. The method of claim 13 , further comprising:
forming an ILD pattern on the substrate,
the ILD pattern including a plurality of holes that expose the substrate;

forming a plurality of contact plugs in the plurality of holes of the ILD pattern;
wherein the forming the stacked structure on the substrate includes,
forming the stacked structure on the ILD pattern, and
forming the lower electrodes on the plurality of contact plugs.

16. The method of claim 13 , further comprising:
forming an upper-electrode hole in the stacked structure by,
patterning an upper one of the two support layers, in which the upper portions of the plurality of lower electrodes are between, before the exposing the sidewalls of the upper portions of the plurality of lower electrodes,
patterning a lower one of the two support layers, in which the upper portions of the plurality of lower electrodes are between, after the etching the exposed sidewalls of the plurality of lower electrodes, and
removing an other of the plurality of mold layers from below the lower one of the two support layers;

forming a capacitor dielectric layer covering surfaces of the plurality of lower electrodes, the capacitor dielectric layer defining voids between the plurality of electrodes; and
forming an upper electrode in the upper-electrode hole of the stacked structure and the voids defined by the capacitor dielectric layer.

17. The method of claim 13 , further comprising:
connecting a controller to the semiconductor memory device formed by the method of claim 16 .

18. The method of claim 1 , wherein the removing the second mold layer occurs after the patterning the second support pattern,
the portions of the sidewalls of the lower electrodes exposed from the removing the second mold layer extend between an upper surface of the first support layer and a lower

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyong-Soo
• Gwak Byoung-Yong
• Yoon Kukhan

Classifications

• H10D1/716

  having vertical extensions · CPC title

• H10D1/692 Primary

  Electrodes · CPC title

• H10D1/042 Primary

  using deposition processes to form electrode extensions · CPC title

• H10B12/30

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title

• H10B12/033 Primary

  the capacitor extending over the transistor · CPC title