Method and apparatus for using universal cavity wafer in wafer level packaging

Patent metadata

Field	Value
Publication number	US-2016365321-A1
Application number	US-201615177723-A
Country	US
Kind code	A1
Filing date	Jun 9, 2016
Priority date	Jun 9, 2015
Publication date	Dec 15, 2016
Grant date	—

Abstract

An electronics module assembly is described herein that packages dies using a universal cavity wafer that is independent of electronics module design. In one embodiment, the electronics module assembly can include a cavity wafer having a single frontside cavity that extends over a majority of a frontside surface area of the cavity wafer and a plurality of fillports. The assembly can also include at least one group of dies placed in the frontside cavity and encapsulant that secures the position of the at least one group of dies relative to the cavity wafer. Further, a layer of the encapsulant can cover a backside of the cavity wafer.

First claim

What is claimed is:

1 . An electronics module assembly, comprising:
a cavity wafer having a single frontside cavity that extends over a majority of a frontside surface area of the cavity wafer, a single backside cavity, and a plurality of fillports; at least one group of dies, where the dies are placed in the frontside cavity; and encapsulant that fills the frontside cavity, the backside cavity, and the fillports, wherein the encapsulant secures the position of the at least one group of dies relative to the cavity wafer.

2 . The electronics module assembly of claim 1 wherein the dies in the at least one group of dies are interconnected to form an electronic module.

3 . The electronics module assembly of claim 1 wherein the frontside cavity is bounded by a full thickness perimeter rim of the cavity wafer.

4 . The electronics module assembly of claim 1 where the plurality of fillports are distributed throughout a fillport area that is an area corresponding to the frontside cavity.

5 . The electronics module assembly of claim 1 wherein the cavity wafer is made of any rigid material that tolerates 230° C. process temperature.

6 . The electronics module assembly of claim 4 , wherein a portion of the fillport area is further cut out and the frontside cavity extends to the space formed by cutting out the portion of the fillport area.

7 . An electronics module assembly, comprising:
a cavity wafer having a single frontside cavity that extends over a majority of a frontside surface area of the cavity wafer and a plurality of fillports; at least one group of dies, where the dies are placed in the frontside cavity; and encapsulant that fills the frontside cavity and the fillports, wherein the encapsulant secures the position of the at least one group of dies relative to the cavity wafer, wherein a uniform layer of the encapsulant covers a backside of the cavity wafer.

8 . The electronics module assembly of claim 7 wherein the dies in the at least one group of dies are interconnected to form an electronic module.

9 . The electronics module assembly of claim 7 wherein the frontside cavity is bounded by a full thickness perimeter rim of the cavity wafer.

10 . The electronics module assembly of claim 7 where the plurality of fillports are distributed throughout a fillport area that is an area corresponding to the frontside cavity.

11 . The electronics module assembly of claim 7 wherein the cavity wafer is made of any rigid material that tolerates 230° C. process temperature.

12 . The electronics module assembly of claim 10 , wherein a portion of the fillport area is further cut out and the frontside cavity extends to the space formed by cutting out the portion of the fillport area.

13 . The electronics module assembly of claim 7 wherein a thickness of the layer of the encapsulant covering the backside of the cavity wafer is determined to minimize wafer bow caused by encapsulant in the frontside cavity.

14 . A method for forming an electronics module assembly, the method comprising:
creating a cavity wafer by etching a wafer to form a single frontside cavity that extends over a majority of a frontside surface area of the wafer and a plurality of fillports; placing at least one group of dies in the frontside cavity; and flowing encapsulant from the backside of the cavity wafer through the fillports and into the frontside cavity to surround the at least one group of dies.

15 . The method of claim 14 , further comprising etching a single backside cavity in the cavity wafer.

16 . The method of claim 14 , further comprising applying heat to the electronics module assembly to cure the encapsulant; and
removing excess encapsulant to the point that the encapsulant fills the backside cavity.

17 . The method of claim 14 , further comprising removing a backside of the cavity wafer to expose the fillports.

18 . The method of claim 17 , further comprising:
applying heat to the electronics module assembly to cure the encapsulant; and removing excess encapsulant from the backside of the cavity wafer to form a uniform layer of the encapsulant on the backside of the cavity wafer.

19 . The method of claim 18 , wherein a thickness of the layer of encapsulant on the backside of the cavity wafer is determined to reduce bowing from encapsulant in the frontside cavity.

20 . The method of claim 18 , further comprising:
removing the layer of encapsulant on the backside of the cavity wafer to reduce bowing from the encapsulant in the frontside cavity.

21 . The method of claim 20 , further comprising:
removing a portion of the cavity wafer at the backside with a uniform thickness to further reduce bowing from the encapsulant in the frontside cavity.

Assignees

• Charles Stark Draper Laboratory Inc

Inventors

• Karpman Maurice
• Rickley Michael
• Mueller Andrew
• Mueller Nicole
• Thompson Jeffrey
• Baab Charles

Classifications

• H10W72/9413

  on encapsulations · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W70/698

  Semiconductor materials that are electrically insulating, e.g. undoped silicon · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W70/681

  comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage · CPC title