SSIC device and link control method for SSIC device

US2016360568A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016360568-A1
Application numberUS-201615132885-A
CountryUS
Kind codeA1
Filing dateApr 19, 2016
Priority dateJun 5, 2015
Publication dateDec 8, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An SSIC (SuperSpeed Inter-Chip) device comprises a detecting circuit operable to execute at least one of a first and a second detection processes and generate a detection result, wherein the first detection process is operable to detect an SSIC compatible object and the second detection process is operable to detect whether the SSIC compatible object satisfies at least one of a de-link state and a re-link state, a control circuit operable to generate a control signal according to the detection result, and a Mobile-Physical-Layer circuit operable to execute at least one of the following steps: if the control signal indicates that the SSIC compatible object is detected and satisfies the de-link state, disconnecting a normal connection between the SSIC device and the SSIC host; and if the control signal indicates that the SSIC compatible object is detected and satisfies the re-link state, connecting the SSIC device with the SSIC host.

First claim

Opening claim text (preview).

What is claimed is: 1 . An SSIC (SuperSpeed Inter-Chip) device capable of actively disconnecting a normal connection between the SSIC device and an SSIC host, comprising: a detecting circuit operable to carry out at least one of a first detection process and a second detection process and generate a detection result accordingly, in which the first detection process is operable to detect an SSIC compatible object and the second detection process is operable to detect whether the SSIC compatible object satisfies a prescribed state including at least one of a de-link state and a re-link state; a control circuit operable to generate a control signal according to the detection result; and an M-PHY (Mobile Physical Layer) circuit operable to carry out at east one of several steps including the following steps: when the control signal indicates that the SSIC compatible object is detected and satisfies the de-link state, actively disconnecting the normal connection between the SSIC device and the SSIC host according to the control signal; and when the control signal indicates that the SSIC compatible object is detected and satisfies the re-link state, actively connecting the SSIC device with the SSIC host according to the control signal. 2 . The SSIC device of claim 1 , wherein the de-link state includes at least one of an unidentifiable state, a non-operational state and an externally-interrupted state, and when the control signal indicates that the SSIC compatible object is detected and satisfies the de-link state, the SSIC device actively disconnects the normal connection with the SSIC host while keeping a physical connection with the SSIC compatible object. 3 . The SSIC device of claim 1 , wherein the several steps further include a step of actively disconnecting the normal connection with the SSIC host according to the control signal when the control signal indicates that the SSIC compatible object is not detected. 4 . The SSIC device of claim 1 , wherein the control circuit is further operable to generate the control signal according to a current state of the SSIC device, and the several steps further include a step of keeping the normal connection with the SSIC host according to the control signal when the control signal indicates that the current state of the SSIC device is a sleeping-mode state and the SSIC compatible object is not detected. 5 . The SSIC device of claim 1 , wherein the control circuit is further operable to generate the control signal according to a current state of the SSIC device, and the several steps further include a step of establishing no connection with the SSIC host according to the control signal when the control signal indicates that the SSIC device does not connect with the SSIC host and the SSIC compatible object is not detected or conforms to the de-link state. 6 . The SSIC device of claim 1 , wherein the normal connection is associated with one of the following modes: an operation mode operable to make the SSIC device and the SSIC host execute normal transmission and reception; a first power-saving mode operable to reduce power consumption of the SSIC device; and a second power-saving mode operable to save the SSIC device more power in comparison with the first power-saving mode. 7 . The SSIC device of claim 1 , wherein both the SSIC device and the SSIC host are included in an SSIC system, and a physical connection relationship between the SSIC device and the SSIC host is kept unchanged regardless of the detection of the SSIC compatible object. 8 . An SSIC (SuperSpeed Inter-Chip) device link control method capable of actively disconnecting a normal connection between an SSIC device and an SSIC host, comprising: carrying out at least one of a first detection process and a second detection process and thereby generating a detection result, in which the first detection process is operable to detect an SSIC compatible object and the second detection process is operable to detect whether the SSIC compatible object satisfies a prescribed state including at least one of a de-link state and a re-link state; generating a control signal according to the detection result; and carrying out at least one of several steps including the following steps: when the control signal indicates that the SSIC compatible object is detected and satisfies the de-link state, actively disconnecting the normal connection between the SSIC device and the SSIC host according to the control signal; and when the control signal indicates that the SSIC compatible object is detected and satisfies the re-link state, actively connecting the SSIC device with the SSIC host according to the control signal. 9 . The SSIC device link control method of claim 8 , wherein the de-link state includes at least one of an unidentifiable state, a non-operational state and an externally-interrupted state, and when the control signal indicates that the SSIC compatible object is detected and satisfies the de-link state, the SSIC device is made to actively disconnect the normal connection with the SSIC host while keeping a physical connection with the SSIC compatible object. 10 . The SSIC device link control method of claim 8 , wherein the several steps further include a step of actively disconnecting the normal connection with the SSIC host according to the control signal when the control signal indicates that the SSIC compatible object is not detected. 11 . The SSIC device link control method of claim 8 , wherein the step of generating the control signal includes a step of generating the control signal according to a current state of the SSIC device, and the several steps further include a step of keeping the normal connection with the SSIC host according to the control signal when the control signal indicates that the current state of the SSIC device is a sleeping-mode state and the SSW compatible object is not detected. 12 . The SSIC device link control method of claim 8 , wherein the step of generating the control signal includes a step of generating the control signal according to a current state of the SSIC device, and the several steps further include a step of establishing no connection with the SSIC host according to the control signal when the control signal indicates that the SSIC device does not connect with the SSIC host and the SSIC compatible object is not detected or conforms to the de-link state. 13 . The SSIC device link control method of claim 8 , wherein the normal connection is associated with one of the following modes: an operation mode operable to make the SSIC device and the SSIC host execute normal transmission and reception; a first power-saving mode operable to reduce power consumption of the SSIC device and allow the SSIC device to return to the operation mode within a first duration; and a second power-saving mode operable to reduce power consumption of the SSIC device and allow the SSIC device to return to the operation mode within a second duration which is longer than the first duration. 14 . The SSIC device link control method of claim 8 , wherein the step of actively disconnecting the normal connection between the SSIC device and the SSIC host is carried out by an M-PHY (Mobile Physical Layer) circuit of the SSIC device and includes the following steps: making a transmitter of the M-PHY circuit of the SSIC device send an interruption request; after sending the interruption request, disabling the transmitter and a receiver of the M-PHY circuit of the SSIC device; and making an LTSSM (Link Training and Status State Machine) of the SSIC device enter a SuperSpeed Disabled state. 15 .

Assignees

Inventors

Classifications

  • Termination or inactivation of sessions, e.g. event-controlled end of session · CPC title

  • in terminal devices · CPC title

  • H04W76/028Primary

    Electricity · mapped topic

  • in the physical layer [OSI layer 1] · CPC title

  • in wireless communication networks · CPC title

Patent family

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Frequently asked questions

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What does patent US2016360568A1 cover?
An SSIC (SuperSpeed Inter-Chip) device comprises a detecting circuit operable to execute at least one of a first and a second detection processes and generate a detection result, wherein the first detection process is operable to detect an SSIC compatible object and the second detection process is operable to detect whether the SSIC compatible object satisfies at least one of a de-link state an…
Who is the assignee on this patent?
Realtek Semiconductor Corp
What technology area does this patent fall under?
Primary CPC classification H04W52/0209. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Dec 08 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).