Inter-chip communications with link layer interface and protocol adaptor

Patent metadata

Field	Value
Publication number	US-9280510-B2
Application number	US-201514600470-A
Country	US
Kind code	B2
Filing date	Jan 20, 2015
Priority date	Mar 30, 2012
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface.

First claim

What is claimed is:

1. An interface between units in a device, comprising:
a link layer system interface to:
communicate between a system and an external device; and
sequence data packets; and

a protocol adaptor to:
function as an intermediate unit between the link layer system interface and a plurality of low power, serial, embedded clock physical layer interfaces;
translate responses at a lower power for inter-chip communications between each connected interface; and
wherein at least two of the plurality of low power, serial, embedded clock physical layers are used to provide a multi-lane configuration.

2. The interface of claim 1 , wherein the protocol adaptor is configured to map SuperSpeed power states for the communications of the protocol adaptor between the high speed, high power link layer system interface and the low power, serial, embedded clock physical layer interfaces.

3. The interface of claim 1 , wherein the protocol adaptor is configured to map a single PIPE3 interface to multiple low power, serial, embedded clock physical layers.

4. The interface of claim 1 , wherein the protocol adaptor comprises:
a transmit scrambler; and
a receive descrambler.

5. The interface of claim 1 , wherein the high speed, high power link layer system interface comprises:
a USB software stack; and
a USB SuperSpeed MAC, comprising:
a protocol layer comprising a USB 3.0 protocol generator; and

a link layer comprising a Link Training Status State Machine (LTSSM).

6. The interface of claim 1 , wherein the protocol adaptor comprises a transmitter Reference M-PHY Module Interface control block (TX RMMI CTRL), configured to:
receive data from a PIPE3 interface of the MAC; and
place the data on an M-TX line on an RMMI interface to low power, serial, embedded clock physical layer.

7. The interface of claim 1 , wherein the protocol adaptor comprises a receiver Reference M-PHY Module Interface control block (RX RMMI CTRL), configured to:
receive data from the M-RX line on an RMMI interface from a low power, serial, embedded clock physical layer;
descramble the data;
concatenate the data; and
place the data on a PIPE3 receive data line.

8. The interface of claim 1 , wherein the low power, serial, embedded clock physical layer is external to the device.

9. The interface of claim 1 , wherein the low power, serial, embedded clock physical layer interfaces are to implement a high bandwidth serial physical layer at different high-speed (HS) gears and rates and support a low-speed (LS) pulse width modulation (PWM) scheme.

10. The interface of claim 1 , wherein a link layer enables a USB 3.0 compliant interface termed PIPE3.

11. The interface of claim 6 , wherein the TX RMMI CTRL is configured to manage multiple lanes in multi-lane configurations.

12. The interface of claim 6 , wherein the TX RMMI CTRL is configured to stripe data across multiple lanes in the RMMI data lines.

13. A method for implementing communications between units in a device, comprising:
receiving link layer packets in a protocol adaptor from a media access controller (MAC), wherein a link layer is to sequence data packets;
scrambling the link layer packets in the protocol adaptor;
sending the scrambled packets to a plurality of low power, serial, embedded clock physical layers for transmission over a serial link at a lower power for inter-chip communications; and
wherein at least two of the plurality of low power, serial, embedded clock physical layers are used to provide a multi-lane configuration.

14. The method of claim 13 , comprising:
receiving scrambled packets in a protocol adaptor from the low power, serial, embedded clock physical layers;
descrambling the scrambled packets to form link layer packets; and
sending the link layer packets to the MAC.

15. The method of claim 13 , comprising establishing communications by issuing Link Training Status State Machine (LTSSM) signals from the protocol adaptor to the MAC to control the communications.

16. The method of claim 13 , comprising training the low power, serial, embedded clock physical layers link from the protocol adaptor without using the training commands issued by the MAC.

17. The method of claim 13 , comprising placing the low power, serial, embedded clock physical layers in a STALL mode without affecting the state of the MAC.

18. The method of claim 13 , comprising moving the low power, serial, embedded clock physical layers link between STALL mode and HS-BURST mode without affecting the state of the MAC.

19. At least one non-transitory machine readable medium comprising instructions stored therein that, in response to being executed on a computing device, cause the computing device to:
issue link training and status state machine (LTSSM) commands to a media access controller; and
issue low power, serial, embedded clock physical layer commands to a low power, serial, embedded clock physical layer.

20. The at least one non-transitory machine readable medium of claim 19 , comprising instructions stored therein that, in response to being executed on a computing device, cause the computing device to:
scramble outgoing packets before sending the packets to a low power, serial, embedded clock physical layer; and
descramble incoming packets from a low power, serial, embedded clock physical layer.

Assignees

• Intel Corp

Inventors

• Ranganathan Sridharan
• Harriman David J
• Mukker Anoop
• Chellappan Satheesh
• Vadivelu Karthi R
• Sharma Shalini
• Sarwar Zeeshan

Classifications

• G06F13/4291 Primary

  using a clocked protocol · CPC title

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• Y02B60/1235

  Cross-Sectional Technologies · mapped topic

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• G06F13/426

  using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus · CPC title