Apparatus, system and method for sharing physical layer logic across multiple protocols

Patent metadata

Field	Value
Publication number	US-9697168-B2
Application number	US-201514668886-A
Country	US
Kind code	B2
Filing date	Mar 25, 2015
Priority date	Mar 25, 2015
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

Techniques and mechanisms to provide common interface logic for multiple protocol engines to access physical layer circuitry at different times. In an embodiment, a state machine of an interface device is to participate in exchanges with physical layer resources on behalf of any of various protocol engines coupled to the interface device via different respective interfaces. Based on state transitions by the state machine, circuitry corresponding to a particular one of such interfaces may selectively send a clock signal for operation of a port controller attempting to access the physical layer circuitry. In some embodiments, multiple interface devices are configured to provide an hierarchical interface architecture for more than two port controllers that variously support at least two protocols.

First claim

What is claimed is:

1. An integrated circuit comprising:
first circuitry including:
a first state machine configured to transition among first states based on both a request for power and a request for a first clock signal each on behalf of a first port controller, the first state machine further to generate a first control signal;
a second state machine configured to transition among second states based on a request for a second clock signal on behalf of the first port controller, wherein a first frequency of the first clock signal is greater than a second frequency of the second clock signal, the second state machine further to generate a second control signal; and
first clock control logic responsive to the first control signal to transmit the first clock signal toward the first port controller, and further responsive to the second control signal to transmit the second clock signal toward the first port controller; and

a third state machine configured to transition among third states based on requests from the first state machine and the second state machine, the third state machine to send from the first circuitry to physical layer circuitry requests on behalf of the first port controller.

2. The integrated circuit of claim 1 , further comprising:
second circuitry to receive requests from a second port controller, the second circuitry to send requests to the third state machine on behalf of the second port controller, wherein the third state machine is configured to transition between the third states in response to requests from either one of the first circuitry and the second circuitry.

3. The integrated circuit of claim 2 , wherein the second circuitry comprises:
a fourth state machine to transition among fourth states based on both a request for power and a request for the first clock signal each on behalf of a second port controller, the fourth state machine to generate a fourth control signal;
a fifth state machine to transition among fifth states based on a request for the second clock signal on behalf of the second port controller, the fifth state machine to generate a fifth control signal; and
second clock control logic to transmit the first clock signal toward the second port controller in response to the fourth control signal and to transmit the second clock signal toward the second port controller in response to the fifth control signal.

4. The integrated circuit of claim 1 , wherein a first functional block of the integrated circuit includes the first circuitry, the integrated circuit further comprising a second functional block, wherein more than two port controllers are coupled to access the physical layer circuitry via a hierarchical interface architecture including the first functional block and the second functional block.

5. The integrated circuit of claim 4 , wherein port controllers each supporting a first protocol are coupled to the first functional block via the second functional block, and wherein another port controller supporting a second protocol is coupled to the first functional block independent of the second functional block.

6. The integrated circuit of claim 1 , wherein the integrated circuit resides on a system-on-chip including the first port controller or the physical layer circuitry.

7. The integrated circuit of claim 1 , wherein the physical layer circuitry is compatible with includes a mobile physical layer (M-PHY) specification.

8. The integrated circuit of claim 1 , wherein the first port controller supports communications compatible with a SuperSpeed USB Inter-chip specification.

9. The integrated circuit of claim 1 , wherein the first port controller supports communications compatible with a Universal Flash Storage specification.

10. The integrated circuit of claim 1 , wherein the first port controller supports communications compatible with a Mobile Peripheral Component Interconnect Express specification.

11. A method at an integrated circuit, the method comprising:
transitioning a first state machine of first circuitry among first states based on both a request for power and a request for a first clock signal each on behalf of a first port controller;
transitioning a second state machine of the first circuitry among second states based on a request for a second clock signal on behalf of the first port controller, wherein a first frequency of the first clock signal is greater than a second frequency of the second clock signal;
in response to a first control signal from the first state machine, transmitting the first clock signal from first clock control logic of the first circuitry toward the first port controller;
in response to a second control signal from the second state machine, transmitting the second clock signal from the first clock control logic of the first circuitry toward the first port controller;
transitioning a third state machine of the first circuitry among third states based on requests from the first state machine and the second state machine; and
sending requests on behalf of the first port controller from the third state machine to physical layer circuitry.

12. The method of claim 11 , further comprising:
with second circuitry of the integrated circuit:
receiving requests from a second port controller; and
sending requests to the third state machine on behalf of the second port controller; and
further transitioning the third state machine between the third states in response to requests from the second circuitry.

13. The method of claim 12 , further comprising:
transitioning a fourth state machine of the second circuitry among fourth states based on both a request for power and a request for the first clock signal each on behalf of a second port controller;
generating a fourth control signal with the fourth state machine;
transitioning a fifth state machine of the second circuitry among fifth states based on a request for the second clock signal on behalf of the second port controller;
generating a fifth control signal with the fifth state machine;
transmitting the first clock signal from second clock control logic of the second circuitry toward the second port controller in response to the fourth control signal; and
transmitting the second clock signal from the second clock control logic toward the second port controller in response to the fifth control signal.

14. The method of claim 11 , wherein a first functional block of the integrated circuit includes the first circuitry, the integrated circuit further comprising a second functional block, wherein more than two port controllers are coupled to access the physical layer circuitry via a hierarchical interface architecture including the first functional block and the second functional block.

15. The method of claim 14 , wherein port controllers each supporting a first protocol are coupled to the first functional block via the second functional block, and wherein another port controller supporting a second protocol is coupled to the first functional block independent of the second functional block.

16. The method of claim 11 , wherein the integrated circuit resides on a system-on-chip including the first port controller or the physical layer circuitry.

17. The method of claim 11 , wherein the physical layer circuitry is compatible with includes a mobile physical layer (M-PHY) specification.

18. A system comprising
an integrated circuit including:
first circuitry comprising:
a first state machine configured to transition among first states based on both a request for power and a request for a first clock sign

Assignees

• Ranganathan Sridharan
• Chellappan Satheesh
• Intel Corp

Inventors

• Ranganathan Sridharan
• Chellappan Satheesh

Classifications

• G06F1/324

  by lowering clock frequency · CPC title

• G06F13/387

  for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system · CPC title

• G06F13/4291 Primary

  using a clocked protocol · CPC title

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• Y02B60/1235

  Cross-Sectional Technologies · mapped topic