Thin film transistor, array substrate and method of manufacturing the same

US2016359047A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016359047-A1
Application numberUS-201514892569-A
CountryUS
Kind codeA1
Filing dateJun 25, 2015
Priority dateJan 22, 2015
Publication dateDec 8, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The disclosed provides a thin film transistor, an array substrate, a display device and methods of manufacturing the thin film transistor and the array substrate. An active layer of the thin film transistor is formed of metallic oxide material, and a source electrode and a drain electrode of the thin film transistor both are formed of graphene or silver nanowire. The source electrode and the drain electrode are formed through an ink-jet printing process. Due to characteristics of graphene or silver nanowire, the manufacturing process of the thin film transistor may be simplified, the performance of the thin film transistor may be improved and the size of a channel region may be decreased. Further, an aperture ratio of the array substrate and the display device having such a thin film transistor may be increased.

First claim

Opening claim text (preview).

1 . A thin film transistor, wherein an active layer of the thin film transistor is formed of metallic oxide material, and a source electrode and a drain electrode of the thin film transistor both are formed of graphene or silver nanowire. 2 . The thin film transistor of claim 1 , wherein the source electrode and the drain electrode of the thin film transistor both are formed of graphene or silver nanowire through an ink-jet printing process. 3 . The thin film transistor of claim 1 , wherein a gate electrode of the thin film transistor is also formed of graphene or silver nanowire. 4 . An array substrate, comprising a plurality of thin film transistors of claim 1 . 5 . The array substrate of claim 4 , further comprising a pixel electrode which is formed of the same material as the drain electrode and is integrally connected thereto. 6 . The array substrate of claim 5 , further comprising: a passivation layer disposed on the pixel electrode; and a common electrode disposed on the passivation layer. 7 . A method of manufacturing a thin film transistor, comprising steps of: forming the thin film transistor on a substrate, wherein an active layer of the thin film transistor is formed of metallic oxide material, and a source electrode and a drain electrode of the thin film transistor both are formed of graphene or silver nanowire. 8 . The method of manufacturing a thin film transistor of claim 7 , wherein the step of forming the source electrode and the drain electrode of the thin film transistor from graphene or silver nanowire comprises: forming the source electrode and the drain electrode through an ink-jet printing process. 9 . The method of manufacturing a thin film transistor of claim 7 , wherein the step of forming the active layer of the thin film transistor from metallic oxide material comprises: doping at least one of gallium ion, tin ion, indium ion and hafnium ion into aluminum oxide based binary metal oxides, zinc oxide based binary metal oxides or indium oxide based binary metal oxides to form the metallic oxide. 10 . A method of manufacturing an array substrate, comprising the method of manufacturing a thin film transistor of claim 7 . 11 . The method of manufacturing an array substrate of claim 10 , wherein the step of forming the source electrode and the drain electrode of the thin film transistor from graphene or silver nanowire comprises: forming the source electrode and the drain electrode through an ink-jet printing process while forming a pixel electrode connected integrally to the drain electrode. 12 . The method of manufacturing an array substrate of claim 10 , wherein the step of forming the source electrode and the drain electrode of the thin film transistor from graphene or silver nanowire further comprises: depositing a transparent conductive layer, which comprises the source electrode, the drain electrode and a pixel electrode connected integrally to the drain electrode, through the ink-jet printing process. 13 . The method of manufacturing an array substrate of claim 10 , wherein the step of forming the thin film transistor on the substrate comprises: forming a gate electrode of the thin film transistor and a gate line connected to the gate electrode from graphene or silver nanowire through an ink-jet printing process. 14 . A display device, comprising the array substrate of claim 4 . 15 . The thin film transistor of claim 2 , wherein the gate electrode of the thin film transistor is also formed of graphene or silver nanowire. 16 . The method of manufacturing a thin film transistor of claim 7 , wherein the step of forming the active layer of the thin film transistor from metallic oxide material comprises: doping at least one of gallium ion, tin ion, indium ion and hafnium ion into aluminum oxide based binary metal oxides, zinc oxide based binary metals oxides or indium oxide based binary metal oxides to form the metallic oxide.

Assignees

Inventors

Classifications

  • Manufacture or treatment · CPC title

  • Subject matter not provided for in other groups of this subclass · CPC title

  • comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

  • using liquid deposition, e.g. printing · CPC title

  • wherein the TFTs are in active matrices · CPC title

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What does patent US2016359047A1 cover?
The disclosed provides a thin film transistor, an array substrate, a display device and methods of manufacturing the thin film transistor and the array substrate. An active layer of the thin film transistor is formed of metallic oxide material, and a source electrode and a drain electrode of the thin film transistor both are formed of graphene or silver nanowire. The source electrode and the dr…
Who is the assignee on this patent?
Boe Technology Group Co Ltd, Hefei Boe Optolectronics Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D30/6755. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Dec 08 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).