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Epitaxial wafer, method for producing the same, photodiode, and optical sensor device
US9171978B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9171978-B2 |
| Application number | US-201414285234-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 22, 2014 |
| Priority date | May 28, 2013 |
| Publication date | Oct 27, 2015 |
| Grant date | Oct 27, 2015 |
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Abstract
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A method for producing an epitaxial wafer includes a step of growing an epitaxial layer structure on a III-V semiconductor substrate, the epitaxial layer structure including a III-V semiconductor multiple-quantum well and a III-V semiconductor surface layer, wherein the step of growing the epitaxial layer structure on the substrate is performed such that a lattice mismatch Δω of the multiple-quantum well with respect to the substrate satisfies a range of −0.13%≦Δω<0% or 0%<Δω≦+0.13%, the range having a center displaced from zero, and an X-ray rocking curve in a zero-order diffraction peak derived from the multiple-quantum well has a full width at half maximum (FWHM) of 30 seconds or less.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for producing an epitaxial wafer, the method comprising: a step of growing an epitaxial layer structure on a III-V semiconductor substrate, the epitaxial layer structure including a III-Vsemiconductor multiple-quantum well and a III-V semiconductor surface layer, wherein the step of growing the epitaxial layer structure on the substrate is performed such that a lattice mismatch Δω of the multiple-quantum well with respect to the substrate satisfie…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9171978B2 cover?
- A method for producing an epitaxial wafer includes a step of growing an epitaxial layer structure on a III-V semiconductor substrate, the epitaxial layer structure including a III-V semiconductor multiple-quantum well and a III-V semiconductor surface layer, wherein the step of growing the epitaxial layer structure on the substrate is performed such that a lattice mismatch Δω of the multiple-qu…
- Who is the assignee on this patent?
- Sumitomo Electric Industries
- What technology area does this patent fall under?
- Primary CPC classification H10F77/1248. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Oct 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).