Large dynamic range rf voltage sensor and method for voltage mode rf bias application of plasma processing systems

Patent metadata

Field	Value
Publication number	US-2016358755-A1
Application number	US-201514728444-A
Country	US
Kind code	A1
Filing date	Jun 2, 2015
Priority date	Jul 21, 2014
Publication date	Dec 8, 2016
Grant date	—

Abstract

A voltage sensor of a substrate processing system including a multi-divider circuit, a clamping circuit and first and second outputs. The multi-divider circuit receives a RF signal indicative of a RF voltage at a substrate. The multi-divider circuit includes dividers of respective channels and outputting first and second reduced voltages based on the received RF signal. The reduced voltages are less than the RF voltage. The clamping circuit clamps the first reduced voltage to a first predetermined voltage when the RF voltage is greater than a second predetermined voltage or the first reduced voltage is greater than a third predetermined voltage. While the received RF signal is in first and second voltage ranges, the first and second outputs output output signals based respectively on the first and second reduced voltages. The first predetermined voltage is based on a maximum value of the first voltage range.

First claim

1 . A voltage sensor of a substrate processing system, the voltage sensor comprising:
a multi-divider circuit configured to receive a radio frequency (RF) signal, wherein the received RF signal is indicative of a RF voltage provided at a substrate in a plasma chamber of the substrate processing system, wherein the multi-divider circuit comprises a first divider and a second divider, wherein the first divider corresponds to a first channel and outputs a first reduced voltage based on the received RF signal, wherein the second divider corresponds to a second channel and outputs a second reduced voltage based on the received RF signal, and wherein the first reduced voltage and the second reduced voltage are less than the RF voltage; a clamping circuit configured to clamp the first reduced voltage to a first predetermined voltage when (i) the RF voltage is greater than a second predetermined voltage, or (ii) the first reduced voltage is greater than a third predetermined voltage; a first output of the first channel configured to output a first output signal based on the first reduced voltage and while the received RF signal is in at least one of a first voltage range or a second voltage range, wherein the second voltage range is higher than the first voltage range, and wherein the first predetermined voltage is based on a maximum value of the first voltage range; and a second output of the second channel configured to output a second output signal based on the second reduced voltage and while the received RF signal is in the at least one of the first voltage range or the second voltage range.

2 . The voltage sensor of claim 1 , wherein:
the first divider comprises a first capacitance connected in series with a second capacitance; and the second divider comprises a third capacitance connected in series with a fourth capacitance.

3 . The voltage sensor of claim 2 , wherein:
the first divider comprises a fifth capacitance and a first resistance connected in parallel with the second capacitance; and the second divider comprises a sixth capacitance and a second resistance connected in parallel with the fourth capacitance.

4 . The voltage sensor of claim 1 , wherein the clamping circuit comprises a pair of zener diodes.

5 . The voltage sensor of claim 1 , wherein:
the first predetermined voltage is equal to the third predetermined voltage; and the second predetermined voltage is greater than the first predetermined voltage and the third predetermined voltage.

6 . The voltage sensor of claim 1 , wherein:
the second channel comprises a buffer circuit; the buffer circuit comprises an amplifier and a voltage divider; the amplifier receives a first input and a second input; the first input is generated based on the second reduced voltage; the second input is generated based on an output of the voltage divider; and the second output signal is generated based on an output of the amplifier.

7 . The voltage sensor of claim 6 , wherein the second channel further comprises a voltage circuit configured to block voltages out of the amplifier that are less than a fourth predetermined voltage.

8 . The voltage sensor of claim 7 , wherein:
the voltage circuit comprises a pair of diodes; and the predetermined voltage is 0V.

9 . The voltage sensor of claim 1 , wherein:
the first channel comprises a first rectifier; the second channel comprises a second rectifier; the first rectifier generates a first rectified signal based on the first reduced voltage; and the second rectifier generates a second rectified signal based on the second reduced voltage.

10 . The voltage sensor of claim 9 , wherein:
the first channel comprises a first buffer circuit; the second channel comprises a second buffer circuit; the first buffer circuit buffers the first rectified signal; and the second buffer circuit buffers the second rectified signal.

11 . A voltage controlled interface comprising:
the voltage sensor of claim 1 ; and a controller configured to control a bias voltage supplied to a substrate support structure in the plasma chamber based on (i) the first output signal while the received RF voltage is in the first voltage range, and (ii) the second output signal while the received RF voltage is in the second voltage range.

12 . A substrate processing system comprising:
the voltage controlled interface of claim 11 ; the plasma chamber; a pickup device configured to receive the RF voltage and generate the RF signal; a chuck disposed in the plasma chamber, wherein the pickup device is connected to the chuck; and a power source configured to supply the bias voltage to the chuck.

13 . A method of operating a voltage sensor of a plasma processing system, the method comprising:
receiving a radio frequency (RF) signal at a first divider and at a second divider, wherein the voltage sensor comprises the first divider and the second divider, wherein the first divider corresponds to a first channel, and wherein the second divider corresponds to a second channel, wherein the received RF signal is indicative of a RF voltage provided at a substrate in a plasma chamber of the plasma processing system; generating a first reduced voltage via the first divider based on the received RF signal; generating a second reduced voltage via the second divider based on the received RF signal, wherein the first reduced voltage and the second reduced voltage are less than the RF voltage; clamping the first reduced voltage to a first predetermined voltage when (i) the RF voltage is greater than a second predetermined voltage, or (ii) the first reduced voltage is greater than a third predetermined voltage; providing at a first output signal via the first channel based on the first reduced voltage and while the received RF signal is in at least one of a first voltage range or a second voltage range, wherein the second voltage range is higher than the first voltage range, and wherein the first predetermined voltage is based on a maximum value of the first voltage range; and providing a second output signal via the second channel based on the second reduced voltage and while the received RF signal is in at least one of the first voltage range or the second voltage range.

14 . The method of claim 13 , further comprising:
filtering the first reduced voltage signal to generate a first filtered output; rectifying the first filtered output, wherein the first output signal is generated based on the first filtered output; filtering the second reduced voltage signal to generate a second filtered output; and rectifying the second filtered output, wherein the second output signal is generated based on the second filtered output.

15 . The method of claim 13 , further comprising receiving at an amplifier a first input and a second input, wherein:
the second channel comprises the amplifier and a voltage divider; the first input is generated based on the second reduced voltage; the second input is generated based on an output of the voltage divider; and the second output signal is generated based on an output of the amplifier.

16 . The method of claim 15 , wherein the second channel further comprises a voltage circuit configured to block voltages out of the amplifier that are less than a fourth predetermined voltage.

17 . The method of claim 13 , further comprising:
generating via a first rectifier a first rectified signal based on the first reduced voltage; and generating via a second rectifier a second rectified signal based on the second reduced voltage, wherein the fi

Assignees

• Lam Res Corp

Inventors

• Long Maolin
• Drewery John
• Paterson Alex

Classifications

• G01R15/04

  Voltage dividers · CPC title

• H01J2237/334

  Etching · CPC title

• G01R19/0084

  Measuring voltage only · CPC title

• H01J37/32155

  Frequency modulation · CPC title

• G01R15/26

  using modulation of waves other than light, e.g. radio or acoustic waves · CPC title