Negative differential resistance circuit element

Patent metadata

Field	Value
Publication number	US-2016351622-A1
Application number	US-201415114010-A
Country	US
Kind code	A1
Filing date	Jan 31, 2014
Priority date	Jan 31, 2014
Publication date	Dec 1, 2016
Grant date	—

Abstract

A circuit component that exhibits a region of negative differential resistance includes: a first layer of material; and a second layer of material in contact with the first layer of material, the contact forming a first self-heating interface. The first self-heating interface is structured such that an electrical current flowing from the first layer of material to the second layer of material encounters an electrical impedance occurring at the first interface that is greater than any electrical impedance occurring in the first and second layers of material, wherein heating occurring at the first interface is dominated by Joule heating caused by the electrical impedance occurring at the first interface, and wherein the electrical impedance occurring at the first interface decreases with increasing temperature to induce a region of negative differential resistance.

First claim

What is claimed is:

1 . A circuit component that exhibits a region of negative differential resistance, comprising:
a first layer of material; and a second layer of material in contact with the first layer of material, the contact forming a first self-heating interface; wherein the first self-heating interface is structured such that an electrical current flowing from the first layer of material to the second layer of material encounters an electrical impedance occurring at the first interface that is greater than any electrical impedance occurring in the first and second layers of material, wherein heating occurring at the first interface is dominated by Joule heating caused by the electrical impedance occurring at the first interface, and wherein the electrical impedance occurring at the first interface decreases with increasing temperature to induce the region of negative differential resistance.

2 . The circuit component of claim 1 , wherein the first layer of material is metallic and the second layer of material is semiconducting.

3 . The circuit component of claim 2 , wherein the thermal energy generated by the first self-heating interface is dominated by Schottky emission and the barrier height at the first self-heating interface is from about 0.1 eV to about 0.5 eV.

4 . The circuit component of claim 1 , wherein the first layer of material is semiconducting and the second layer of material is semiconducting.

5 . The circuit component of claim 1 , further comprising a third layer of material in contact with the second layer of material, the contact forming a second self-heating interface, wherein the second self-heating interface is structured such that an electrical current flowing from the third layer of material to the second layer of material encounters an electrical impedance occurring at the second interface that s greater than any electrical impedance occurring in the third and second layers of material, wherein heating occurring at the second interface is dominated by Joule heating caused by the electrical impedance occurring at the second interface, and wherein the electrical impedance occurring at the second interface decreases with increasing temperature to induce a radon of negative differential resistance.

6 . A self-heating negative differential resistance circuit component, comprising:
a first layer of metallic material; a second layer of semiconductor or insulator material in contact with the first layer of metallic material, the contact forming a first self-heating interface having a first electrical impedance; wherein the first self-heating interface is structured such that an electrical current flowing from the first layer of material to the second layer of material through the first self-heating interface results in generation of thermal energy by the first self-heating interface that is greater than any generation of thermal energy occurring in the first and second layers of material due to bulk heating; wherein the thermal energy generated by the first self-heating interface is dominated by Schottky emission and the barrier height at the first is heating interface is from about 0.1 eV to about 0.5 eV; and wherein the first electrical impedance decreases with increasing temperature to induce a region of negative differential resistance.

7 . The circuit component of claim 6 , wherein the first layer of metallic material and the second layer of material are selected from the croup consisting of TiN—NbO 2 , TaN—NbO 2 , W—Ge, Pb—Ge, Al—Ge, Ni—Ge, Au—GaAs, Au—InSb, Ag—InSb, Au—InAs, Ni—CdS(n), Cu—CdS(n), Pt—CdSe(n), Cu—CdSe(n), Ag—CdSe(n), Ta—ZnO, In—ZnO and Cu—ZnO.

8 . The circuit component of claim further comprising a third layer of material, the third layer of material being metallic and in contact with the second layer of material, the contact forming a second self-heating interface having a second electrical impedance, wherein the second self-heating interface is structured such that an electrical current flowing from the third layer of material to the second layer of material through the second self-heating interface results in generation of thermal energy by the second self-heating interface that is greater than any generation of thermal energy occurring in the third and second layers of material due to bulk heating and wherein the second electrical impedance decreases with increasing temperature to induce a region of negative differential resistance.

9 . The circuit component of claim 8 , wherein the first layer of metallic material comprises TiN, the second layer of material comprises NbO 2 and third layer of material comprises TiN.

10 . The circuit component of claim 8 , wherein the component: configured to operate as a selector in a memory structure.

11 . A method of interfacial heating in a self-heating negative differential resistance circuit component, comprising:
providing a first layer of material and a second layer of material in contact with the first layer of material, the contact forming a first self-heating interface structured such that an electrical current flowing from the first layer of material to the second layer of material encounters an electrical impedance occurring at the first self-heating interface that is greater than any electrical impedance occurring in the first and second layers of material, wherein heating occurring at the first self-heating interface is dominated by Joule heating caused by the electrical impedance occurring at the first self-heating interface, and wherein the electrical impedance occurring at the first self-heating interface decreases with increasing temperature to induce a region of negative differential resistance; and providing an electrical current flowing from the first layer of material to the second layer of material through the first self-heating interface.

12 . The method of claim 11 , wherein the first layer of material is metallic and the second layer of material is semiconducting.

13 . The method of claim 12 , wherein the thermal energy generated by the first self-heating interface is dominated by Schottky emission and the barrier height at the first self-heating interface is from about 0.1 eV to about 0.5 eV.

14 . The method of claim 11 , wherein the first layer of material is semiconducting and the second layer of material is semiconducting.

15 . The method of claim 11 , wherein thermal energy generated by the first self-heating interface is at least about twice as great as any generation of thermal energy occurring in the first and second layers of material due to bulk heating.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Gibson Gary
• Jackson Warren
• Williams R Stanley

Classifications

• H01L27/2418 Primary

  Electricity · mapped topic

• H01L45/1286

  Electricity · mapped topic

• G11C13/003

  Cell access · CPC title

• H01L45/145

  Electricity · mapped topic

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title