Self-aligned source and drain regions for semiconductor devices

Patent metadata

Field	Value
Publication number	US-2016336418-A1
Application number	US-201615224035-A
Country	US
Kind code	A1
Filing date	Jul 29, 2016
Priority date	Mar 12, 2015
Publication date	Nov 17, 2016
Grant date	—

Abstract

A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a gate conductor formed on a substrate; and a deposited doped layer formed in recesses adjacent to the gate conductor and extending along sidewalls of the gate conductor to form vertical portions, the doped layer forming source and drain regions for the semiconductor device; the gate conductor being shaped between the vertical portions to permit formation of a dielectric material between the gate conductor and the vertical portions.

2 . The device as recited in claim 1 , wherein the gate conductor includes a trapezoidal shape.

3 . The device as recited in claim 1 , wherein the vertical portions have a height over the substrate greater than a height of the gate conductor over the substrate.

4 . The device as recited in claim 1 , further comprising a dielectric material formed in gaps between the sidewalls of the gate conductor and the vertical portions of the doped layer.

Assignees

• IBM

Inventors

• De Souza Joel P
• Hekmatshoartabari Bahman
• Kim Jeehwan
• Maurer Siegfried L
• Sadana Devendra K

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P50/262

  by physical means only · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P32/1408

  from or through or into an external applied layer, e.g. photoresist or nitride layers · CPC title