Alignment monitoring structure and alignment monitoring method for semiconductor devices

Patent metadata

Field	Value
Publication number	US-2016336240-A1
Application number	US-201514709889-A
Country	US
Kind code	A1
Filing date	May 12, 2015
Priority date	May 12, 2015
Publication date	Nov 17, 2016
Grant date	—

Abstract

The present disclosure provides in various aspects an alignment monitoring structure and method for monitoring the alignment between a target gate conductor and the corresponding target contact in a semiconductor device, for example, in a CMOS. In accordance with some illustrative embodiments herein, a structure with a plurality of gate conductors disposed over the substrate so as to define a row of parallel gate conductors and a plurality of first contacts is provided, wherein each of the first contacts is disposed between two adjacent gate conductors so as to define a first lateral distance between a first gate conductor and the first contact and a second lateral distance between the first contact and a second gate conductor, and wherein the first lateral distance and the second lateral distance vary systematically along the row of parallel gate conductors.

First claim

1 . An alignment monitoring structure for a semiconductor device, said alignment monitoring structure comprising:
a semiconductor substrate; a plurality of gate conductors disposed over said substrate so as to define a row of parallel gate conductors; and a plurality of first contacts, wherein each of said first contacts is disposed between two adjacent gate conductors so as to define a first lateral distance between a first gate conductor and said first contact and a second lateral distance between said first contact and a second gate conductor and wherein said first lateral distance and said second lateral distance vary systematically along said row of parallel gate conductors.

2 . The alignment monitoring structure of claim 1 , wherein a lateral distance between adjacent gate conductors is constant along said row of parallel gate conductors.

3 . The alignment monitoring structure of claim 1 , wherein said first lateral distance increases along said row of parallel gate conductors.

4 . The alignment monitoring structure of claim 1 , wherein said first lateral distance increases linearly along said row of parallel gate conductors.

5 . The alignment monitoring structure of claim 1 , wherein a first gate conductor of said row of parallel gate conductors is in contact with a corresponding first of said plurality of first contacts so that said first lateral distance between said first gate conductor of said row of parallel gate conductors and said first of said plurality of first contacts is zero.

6 . The alignment monitoring structure of claim 1 , wherein a last gate conductor of said row of parallel gate conductors is in contact with a corresponding last of said plurality of first contacts so that said second lateral distance between said last gate conductor of said row of parallel gate conductors and said last of said plurality of first contacts is zero.

7 . The alignment monitoring structure of claim 1 , wherein said first lateral distance varies from zero to a maximum first lateral distance along said row of parallel gate conductors so that said second lateral distance varies from a maximum second lateral distance to zero along the same direction along said row of parallel gate conductors.

8 . The alignment monitoring structure of claim 7 , wherein said maximum first lateral distance is equal to or less than a lateral distance between adjacent gate conductors.

9 . The alignment monitoring structure of claim 1 , wherein each of said plurality of first contacts is in contact with a layer of insulating material.

10 . The alignment monitoring structure of claim 1 , further comprising a plurality of second contacts, wherein each of said second contacts is in contact with one of said gate conductors.

11 . The alignment monitoring structure of claim 1 , wherein said plurality of gate conductors are electrically connected to each other.

12 . The alignment monitoring structure of claim 11 , wherein said plurality of gate conductors are electrically connected to each other by means of a contact stripe extending along the entire row of parallel gate conductors.

13 . The alignment monitoring structure of claim 1 , wherein said plurality of gate conductors and said plurality of first contacts are positioned above a layer of insulating material.

14 . (canceled)

15 . (canceled)

16 . (canceled)

17 . An alignment monitoring structure for a semiconductor device, said alignment monitoring structure comprising:
a semiconductor substrate; a plurality of gate conductors disposed over said substrate so as to define a row of parallel gate conductors, wherein a lateral distance between adjacent gate conductors is constant along said row of parallel gate conductors; and a plurality of first contacts, wherein each of said first contacts is disposed between two adjacent gate conductors so as to define a first lateral distance between a first gate conductor and said first contact and a second lateral distance between said first contact and a second gate conductor and wherein said first lateral distance and said second lateral distance vary systematically along said row of parallel gate conductors, wherein said first lateral distance increases linearly along said row of parallel gate conductors in a first direction and said second lateral distance decreases linearly along said row of parallel gate conductors in said first direction.

18 . The alignment monitoring structure of claim 17 , wherein:
a first gate conductor of said row of parallel gate conductors is in contact with a corresponding first of said plurality of first contacts so that said first lateral distance between said first gate conductor of said row of parallel gate conductors and said first of said plurality of first contacts is zero; and a last gate conductor of said row of parallel gate conductors is in contact with a corresponding last of said plurality of first contacts so that said second lateral distance between said last gate conductor of said row of parallel gate conductors and said last of said plurality of first contacts is zero.

19 . The alignment monitoring structure of claim 17 , wherein said first lateral distance varies from zero to a maximum first lateral distance along said row of parallel gate conductors so that said second lateral distance varies from a maximum second lateral distance to zero along the same direction along said row of parallel gate conductors.

20 . The alignment monitoring structure of claim 19 , wherein said maximum first lateral distance and said maximum second lateral distance are each equal to or less than said lateral distance between adjacent gate conductors.

21 . The alignment monitoring structure of claim 18 , further comprising a plurality of second contacts, wherein each of said second contacts is in contact with one of said gate conductors.

22 . The alignment monitoring structure of claim 18 , wherein said gate conductors are electrically connected to each other.

23 . The alignment monitoring structure of claim 22 , wherein said gate conductors are electrically connected to each other by means of a contact stripe extending along the entire row of parallel gate conductors.

24 . The alignment monitoring structure of claim 23 , wherein said plurality of gate conductors and said plurality of first contacts are positioned above a layer of insulating material.

25 . An alignment monitoring structure for a semiconductor device, said alignment monitoring structure comprising:
a semiconductor substrate; a plurality of gate conductors disposed over said substrate so as to define a row of parallel gate conductors, wherein a lateral distance between adjacent gate conductors is constant along said row of parallel gate conductors; a conductive contact stripe extending along the entire row of parallel gate conductors that electrically couples each of the plurality of parallel gate conductors to one another: a plurality of first contacts, wherein:
each of said first contacts is disposed between two adjacent gate conductors so as to define a first lateral distance between a first gate conductor and said first contact and a second lateral distance between said first contact and a second gate conductor, said first lateral distance increases linearly along said row of parallel gate conductors in a first direction and said second lateral distance decreases linearly along said row of parallel gate conductors in said first dir

Assignees

• Globalfoundries Inc

Inventors

• Olligs Dominik

Classifications

• H10P74/27

  Structural arrangements therefor · CPC title

• H10W46/501

  for use before dicing · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title