Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2016240666-A1
Application number	US-201514717526-A
Country	US
Kind code	A1
Filing date	May 20, 2015
Priority date	Feb 18, 2015
Publication date	Aug 18, 2016
Grant date	—

Abstract

A device includes a first and a second semiconductor-layer. The second semiconductor-layer is on the first semiconductor-layer, and has a first and a second side-surface. A first gate-dielectric is on the first semiconductor-layer. A second gate-dielectric is on the first side-surface. A gate has a bottom surface facing the first semiconductor-layer, and a third side-surface facing the first side-surface. A first diffusion-layer of a first conductivity-type is in a region in the second semiconductor-layer on a side of the second side-surface, and forms a junction with a region in the second semiconductor-layer on a side of the first side-surface. A silicide is on the second side-surface. A source of the first conductivity-type is in the first semiconductor-layer on a side of the third side-surface. A drain layer of a second conductivity-type is in the first semiconductor-layer on a side of a fourth side-surface of the gate electrode.

First claim

1 . A semiconductor device comprising:
a first semiconductor layer; a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having a first side surface and a second side surface on an opposite side to the first side surface; a first gate dielectric film on the first semiconductor layer; a second gate dielectric film on the first side surface of the second semiconductor layer; a gate electrode having a bottom surface facing a surface of the first semiconductor layer via the first gate dielectric film, and a third side surface facing the first side surface of the second semiconductor layer via the second gate dielectric film; a first diffusion layer of a first conductivity type in a region of the second semiconductor layer on a side of the second side surface, the first diffusion layer forming a junction part with a region of the second semiconductor layer on a side of the first side surface; a silicide layer on the second side surface of the second semiconductor layer, the silicide layer connecting to the first diffusion layer; a source layer of the first conductivity type in the first semiconductor layer on a side of the third side surface of the gate electrode, the source layer being electrically connected to the first diffusion layer and the silicide layer; and a drain layer of a second conductivity type in the first semiconductor layer on a side of a fourth side surface of the gate electrode on an opposite side to the third side surface.

2 . The device of claim 1 , wherein a length along the second side surface from a bottom surface of the silicide layer to a top surface of the silicide layer is larger than a length along the third side surface from the bottom surface of the gate electrode to the top surface of the silicide layer.

3 . The device of claim 1 , wherein a bottom surface of the silicide layer is located at a position deeper than the surface of the first semiconductor layer.

4 . The device of claim 1 , wherein a film thickness of the second gate dielectric film is equal to or smaller than that of the first gate dielectric film.

5 . The device of claim 1 , wherein a film thickness of the second gate dielectric film is smaller than that of the first gate dielectric film.

6 . The device of claim 1 , wherein the gate electrode is formed of a metal having a lower melting point than that of a metal contained in the silicide layer.

7 . The device of claim 1 , wherein an impurity concentration of the first diffusion layer is high in a vicinity of the second side surface and decreases from the second side surface toward the first side surface.

8 . The device of claim 1 , wherein
the region of the second semiconductor layer on the side of the first side surface is a second conductivity-type semiconductor or an intrinsic semiconductor, and the junction part is a PN junction or a PI junction along the second side surface of the second semiconductor layer.

9 . The device of claim 1 , wherein an impurity concentration of the first diffusion layer is higher than that of the source layer.

10 . The device of claim 1 , wherein the first diffusion layer and the silicide layer are located also on the source layer.

11 . The device of claim 1 , wherein the first diffusion layer is a diffusion layer containing arsenic as impurities.

12 . The device of claim 1 , wherein
the first diffusion layer is a diffusion layer containing boron as impurities, and the silicide layer includes a cobalt silicide.

13 . A manufacturing method of a semiconductor device, the method comprising:
forming a first gate dielectric film on a first semiconductor layer, forming a gate electrode on the first gate dielectric film; forming a source layer of a first conductivity type in the first semiconductor layer on one side of the gate electrode; forming a drain layer of a second conductivity type in the first semiconductor layer on other side of the gate electrode; forming a second gate dielectric film on a side surface of the gate electrode on the one side; forming a second semiconductor layer of which a first side surface faces the side surface of the gate electrode via the second gate dielectric film; introducing first conductivity-type impurities to a second side surface of the second semiconductor layer on an opposite side to the first side surface; and forming a silicide layer on the second side surface of the second semiconductor layer, to which the first conductivity-type impurities are introduced.

14 . The method of claim 13 , wherein
formation of the second semiconductor layer comprises: growing a material of the second semiconductor layer on the first semiconductor layer to be in contact with the second gate dielectric film; and etching the material of the second semiconductor layer using a sidewall film as a mask, the sidewall film being provided on the side surface of the gate electrode via the second gate dielectric film, and removing also an upper portion of the first semiconductor layer in a formation region of the source layer.

15 . The method of claim 14 , wherein a bottom surface of the silicide layer is formed at a position deeper than a surface of the first semiconductor layer.

16 . The method of claim 13 , wherein a thickness of the second gate dielectric film is equal to or smaller than that of the first gate dielectric film.

17 . The method of claim 13 , wherein the first conductivity-type impurities are segregated along the silicide layer during formation of the silicide layer.

18 . A manufacturing method of a semiconductor device, the method comprising:
forming a sacrifice gate electrode above a first semiconductor layer; forming a source layer of a first conductivity type in the first semiconductor layer on one side of the sacrifice gate electrode; forming a drain layer of a second conductivity type in the first semiconductor layer on other side of the sacrifice gate electrode; forming a second semiconductor layer of which a first side surface faces a side surface of the sacrifice gate electrode on the one side; introducing first conductivity-type impurities to a second side surface of the second semiconductor layer on an opposite side to the first side surface; forming a silicide layer on the second side surface of the second semiconductor layer, to which the first conductivity-type impurities are introduced; removing the sacrifice gate electrode after formation of the silicide layer to form a gate trench; and forming a gate electrode in the gate trench to be in contact with a first gate dielectric film formed on the first semiconductor layer and with a second gate dielectric film formed on the first side surface of the second semiconductor layer.

19 . The method of claim 18 , further comprising forming the first gate dielectric film on the first semiconductor layer and the second gate dielectric film on the first side surface of the second semiconductor layer in the gate trench, after removing the sacrifice gate electrode.

20 . The method of claim 18 , further comprising:
forming the first gate dielectric film on the first semiconductor layer, before formation of the sacrifice gate electrode; and forming the second gate dielectric film on the first side surface of the second semiconductor layer in the gate trench, after removing the sacrifice gate electrode.

Assignees

• Toshiba Kk

Inventors

• Miyata Toshitaka
• Kondo Yoshiyuki

Classifications

• H10D12/211 Primary

  Gated diodes · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title

• H10D62/142

  Anode regions of thyristors or collector regions of gated bipolar-mode devices · CPC title

• H10D62/151 Primary

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H01L29/66666

  Electricity · mapped topic