Semiconductor structure with integrated passive structures

Patent metadata

Field	Value
Publication number	US-2016307918-A1
Application number	US-201615196681-A
Country	US
Kind code	A1
Filing date	Jun 29, 2016
Priority date	Sep 26, 2012
Publication date	Oct 20, 2016
Grant date	—

Abstract

A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

First claim

What is claimed:

1 . A method, comprising:
forming a high-k dielectric material on a semiconductor material; forming a metal gate material on the high-k material; forming a semiconductor layer on the metal gate material; forming a stacked structure in an active region by patterning the semiconductor material, high-k dielectric material, metal gate material and semiconductor layer; forming a liner on a top and side surfaces of the stacked structure in the active region, and exposed surfaces of a buried oxide layer or bulk silicon; forming an insulator layer over the liner; planarizing the insulator layer to form insulator regions, separated by the stacked structure formed in the active region; recessing the insulator regions to form STI structures; forming a second semiconductor material over the STI structures and the semiconductor layer of the stacked structure in the active region; and performing well implantation processes through the second semiconductor material.

2 . The method of claim 1 , wherein the metal gate material is one of TiN, TaN, Al, and W deposited to a thickness ranging from about 1 nm to about 200 nm.

3 . The method of claim 1 , wherein the semiconductor layer is polysilicon or amorphous silicon, and is 5 nm to 200 nm in thickness.

4 . The method of claim 1 , wherein the patterning is two or more reactive ion chemistries.

5 . The method of claim 1 , wherein the semiconductor material is provided on a buried oxide layer.

6 . The method of claim 1 , wherein the semiconductor material is one of Si, SiGe, SiC Ge, and GeAs.

7 . The method of claim 1 , wherein the forming the stacked structure includes forming openings on opposite sides of the active region.

8 . The method of claim 1 , wherein the planarizing the insulator layer to form insulator regions includes performing a chemical mechanical polishing (CMP) processes on the insulator layer.

Assignees

• IBM

Inventors

• Chou Anthony I
• Kumar Arvind
• Mo Renee T
• Narasimha Shreesh

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P95/064

  the removal being chemical etching · CPC title

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P70/237

  the processing being a planarisation of insulating layers · CPC title

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title