Stage circuit and scan driver using the same

Patent metadata

Field	Value
Publication number	US-2016307537-A1
Application number	US-201615042029-A
Country	US
Kind code	A1
Filing date	Feb 11, 2016
Priority date	Apr 14, 2015
Publication date	Oct 20, 2016
Grant date	—

Abstract

There is provided a stage circuit capable of minimizing a mounting area. The stage circuit includes: an output unit configured to supply a voltage of a first node, an i-th (i is a natural number) carry signal, and to supply an i-th scan signal in response to the voltage of the first node, a voltage of a second node, and a first clock signal, a controller configured to control the voltage of the second node in response to the first clock signal; a pull-up unit configured to control the voltage of the first node in response to a carry signal of a previous stage and a voltage of a first node of the previous stage, and a pull-down unit configured to control the voltage of the first node in response to the voltage of the second node and a carry signal of a next stage.

First claim

What is claimed is:

1 . A stage circuit comprising;
an output unit configured to supply a voltage of a first node to a first output terminal, to supply an i-th (i is a natural number) carry signal to a second output terminal, and to supply an i-th scan signal to a third output terminal in response to the voltage of the first node, a voltage of a second node, and a first clock signal supplied to a first input terminal; a controller configured to control the voltage of the second node in response to the first clock signal supplied to the first input terminal; a pull-up unit configured to control the voltage of the first node in response to a carry signal of a previous stage supplied to a second input terminal and a voltage of a first node of the previous stage supplied to a third input terminal; and a pull-down unit configured to control the voltage of the first node in response to the voltage of the second node and a carry signal of a next stage supplied to a fourth input terminal.

2 . The stage circuit of claim 1 , wherein, when the carry signal of the previous stage is supplied, the second input terminal is set to have a lower voltage than that of the third input terminal.

3 . The stage circuit of claim 1 , wherein the pull-up unit comprises a first transistor having a first electrode connected to the second input terminal, a second electrode connected to the first node, and a gate electrode connected to the third input terminal.

4 . The stage circuit of claim 3 , wherein the pull-up unit further comprises:
a second transistor having a first electrode and a gate electrode connected to the second electrode of the first transistor and a second electrode connected to the first node; and a third transistor having a first electrode connected to the second electrode of the first transistor and a gate electrode and a second electrode connected to the second output terminal.

5 . The stage circuit of claim 4 , wherein the pull-up unit further comprises a fourth transistor having a first electrode and a gate electrode connected to the second input terminal and a second electrode connected to the first electrode of the first transistor.

6 . The stage circuit of claim 3 , wherein the pull-up unit further comprises:
a second transistor having a first electrode and a gate electrode connected to the second electrode of the first transistor and a second electrode connected to the first node; a third transistor having a first electrode connected to the first electrode of the first transistor and a gate electrode and a second electrode connected to the second output terminal; and a fourth transistor having a first electrode and a gate electrode connected to the second input terminal and a second electrode connected to the first electrode of the first transistor.

7 . The stage circuit of claim 1 , further comprising:
a first power source input terminal configured to receive a first off voltage; and a second power source input terminal configured to receive a second off voltage different from the first off voltage.

8 . The stage circuit of claim 7 , wherein the second off voltage is set to be lower than the first off voltage.

9 . The stage circuit of claim 7 , wherein the output unit comprises:
a fifth transistor connected between the first input terminal and the second output terminal and having a gate electrode connected to the first node; a sixth transistor connected between the second output terminal and the second power source input terminal and having a gate electrode connected to the second node; a seventh transistor connected between the first input terminal and the third output terminal and having a gate electrode connected to the first node; an eighth transistor connected between the third output terminal and the first power source input terminal and having a gate electrode connected to the second node; and a ninth transistor connected between the third output terminal and the first power source input terminal and having a gate electrode connected to the fourth input terminal.

10 . The stage circuit of claim 7 , wherein the controller comprises:
a tenth transistor having a first electrode and a gate electrode connected to the first input terminal; an 11 th transistor connected between a second electrode of the tenth transistor and the second power source input terminal and having a gate electrode connected to the second output terminal; a 12 th transistor connected between the first input terminal and the second node and having a gate electrode connected to the second electrode of the tenth transistor; and a 13 th transistor connected between the second node and the second power source input terminal and having a gate electrode connected to the second output terminal.

11 . The stage circuit of claim 7 , wherein the pull-down unit comprises:
a 14 th transistor and a 15 th transistor serially connected between the first node and the second power source input terminal and having gate electrodes connected to the second node; a 16 th transistor connected between the second output terminal and the second power source input terminal and having a gate electrode connected to the fourth input terminal; and a 17 th transistor and an 18 th transistor serially connected between the first node and the second power source input terminal and having gate electrodes connected to the fourth input terminal.

12 . The stage circuit of claim 1 ,
wherein a carry signal of the previous stage is an (i−1)-th carry signal, and wherein a carry signal of the next stage is an (i+1)-th carry signal.

13 . A scan driver including stages respectively connected to scan lines and outputting one of a plurality of clock signals input from an external source as scan signals, wherein an i-th (i is a natural number) stage circuit among the stages comprises:
an output unit configured to supply a voltage of a first node to a first output terminal, to supply an i-th carry signal to a second output terminal, and to supply an i-th scan signal to a third output terminal in response to the voltage of the first node, a voltage of a second node, and a first clock signal supplied to a first input terminal; a controller configured to control the voltage of the second node in response to the first clock signal supplied to the first input terminal; a pull-up unit configured to control the voltage of the first node in response to an (i−1)-th carry signal of a previous stage supplied to a second input terminal and a voltage of a first node of the previous stage supplied to a third input terminal; and a pull-down unit configured to control the voltage of the first node in response to the voltage of the second node and an (i+1)-th carry signal of a next stage supplied to a fourth input terminal.

14 . The scan driver of claim 13 , wherein, when the (i−1)-th carry signal is supplied, the second input terminal is set to have a lower voltage than that of the third input terminal.

15 . The scan driver of claim 13 , wherein the pull-up unit comprises a first transistor having a first electrode connected to the second input terminal, a second electrode connected to the first node, and a gate electrode connected to the third input terminal.

16 . The scan driver of claim 15 , wherein the pull-up unit further comprises:
a second transistor having a first electrode and a gate electrode connected to the second electrode of the first transistor and a second electrode connected to the first node; and a third transistor having a first electrode connected to the second electrode of the first transisto

Assignees

• Samsung Display Co Ltd

Inventors

• Park Jun Hyun
• Kim Sung Hwan
• Song Se Young
• Shin Kyoung Ju
• Lim Jae Keun

Classifications

• G09G2310/0289

  Details of voltage level shifters arranged for use in a driving circuit · CPC title

• G09G3/3696 Primary

  Generation of voltages supplied to electrode drivers · CPC title

• H03K17/6871

  the output circuit comprising more than one controlled field-effect transistor · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title