Transistor and liquid crystal display device having the same

Patent metadata

Field	Value
Publication number	US-2016204136-A1
Application number	US-201514968634-A
Country	US
Kind code	A1
Filing date	Dec 14, 2015
Priority date	Jan 9, 2015
Publication date	Jul 14, 2016
Grant date	—

Abstract

A transistor and a liquid crystal display device having the same are provided. The transistor includes a first gate electrode disposed on a base substrate; a gate insulating layer disposed on the first gate electrode; a semiconductor layer disposed on the gate insulating layer, and including a channel area; a source electrode and a drain electrode connected to both ends of the semiconductor layer; a passivation layer configured to cover the semiconductor layer, the source electrode, and the drain electrode; and a second gate electrode disposed on the passivation layer, and partially overlapping the channel area in a direction from the drain electrode toward the source electrode.

First claim

What is claimed is:

1 . A transistor comprising:
a first gate electrode disposed on a base substrate; a gate insulating layer disposed on the first gate electrode; a semiconductor layer disposed on the gate insulating layer, and including a channel area; a source electrode and a drain electrode connected to both ends of the semiconductor layer; a passivation layer configured to cover the semiconductor layer, the source electrode, and the drain electrode; and a second gate electrode disposed on the passivation layer, and partially overlapping the channel area in a direction from the drain electrode toward the source electrode.

2 . The transistor of claim 1 , wherein an overlap ratio between the gate electrode and the channel area is equal to or more than 20% and less than 100% of a length of the channel area.

3 . The transistor of claim 2 , wherein the overlap ratio between the gate electrode and the channel area is equal to or more than 20% and less than 60% of the length of the channel area.

4 . The transistor of claim 2 , wherein the second gate electrode is disposed on the passivation layer, and contacts the drain electrode through a contact hole exposing the drain electrode.

5 . The transistor of claim 2 , wherein the second gate electrode comprises one of a transparent conductive oxide and a low resistive metal.

6 . The transistor of claim 5 , wherein the low resistive metal comprises one of MoTi, Cu, MoNb, Mo, Cr, and AlNd.

7 . The transistor of claim 2 , wherein the semiconductor layer comprises an oxide semiconductor material.

8 . A liquid crystal display device comprising:
a liquid crystal display panel including a first substrate divided into a display portion and a peripheral portion, a second substrate facing the first substrate in the display portion, and a liquid crystal layer interposed between the first substrate and the second substrate; and a gate driving part disposed on the first substrate in the peripheral portion, wherein the gate driving part comprises: a pull-up control part configured to apply any one carry signal among previous stages to a first node in response to the one carry signal among the previous stages; a pull-up part configured to output a clock signal as an N th gate output signal in response to the signal applied to the first node; a carry part configured to output the clock signal as an N th carry signal in response to the signal applied to the first node; a first pull-down part including a plurality of transistors connected in series, and configured to pull down the first node to a second off signal in response to any one carry signal among next stages; and a second pull-down part configured to pull down the N th gate output signal as a first off signal in response to the one carry signal among the next stages, and wherein the pull-up control part comprises a transistor, and the transistor includes a first gate electrode and a first source electrode connected to a terminal which applies the one carry signal among the previous stages, and a first drain electrode and a second gate electrode connected to the first node.

9 . The liquid crystal display device of claim 8 , wherein the first and second gate electrodes are first and second control electrodes, and the first source electrode is an input electrode, and the first drain electrode is an output electrode.

10 . The liquid crystal display device of claim 9 , wherein in the display portion, the first substrate comprises:
a thin film transistor formed on a base substrate; a first passivation layer disposed on the thin film transistor; a common electrode disposed on the first passivation layer; a second passivation layer disposed on the common electrode; and a pixel electrode disposed on the second passivation layer.

11 . The liquid crystal display device of claim 10 , wherein the thin film transistor comprises:
a third gate electrode formed on the base substrate; a gate insulating layer configured to cover the third gate electrode; a first semiconductor layer disposed on the gate insulating layer; and a second source electrode and a second drain electrode connected to both end portions of the first semiconductor layer, wherein the gate insulating layer, the first passivation layer, and the second passivation layer extend toward the peripheral portion.

12 . The liquid crystal display device of claim 11 , wherein the transistor comprises:
the first gate electrode disposed on the base substrate; a second semiconductor layer disposed on the gate insulating layer, and including a channel area; the first source electrode and the first drain electrode connected to both ends of the first semiconductor layer; and a second gate electrode disposed on the first passivation layer, and configured to overlap a portion of the channel area in a direction from the first drain electrode toward the first source electrode.

13 . The liquid crystal display device of claim 12 , wherein an overlap ratio between the gate electrode and the channel area is equal to or more than 20% and less than 100% of a length of the channel area.

14 . The liquid crystal display device of claim 13 , wherein the overlap ratio between the gate electrode and the channel area is equal to or more than 20% and less than 60% of the length of the channel area.

15 . The liquid crystal display device of claim 13 , wherein the second gate electrode is disposed on the first passivation layer, and contacts the drain electrode through a contact hole exposing the drain electrode.

16 . The liquid crystal display device of claim 13 , wherein the second gate electrode comprises one of a transparent conductive oxide and a low resistive metal.

17 . The liquid crystal display device of claim 16 , wherein the low resistive metal comprises one of MoTi, Cu, MoNb, Mo, Cr, and AlNd.

18 . The liquid crystal display device of claim 13 , wherein the semiconductor layer comprises an oxide semiconductor material.

Assignees

• Samsung Display Co Ltd

Inventors

• Takeuchi Noboru
• Kang Min-Soo
• Kim Beom-Jun
• Kim Yoon-Ho
• Syn Seong-Yeol
• Lee Hong-Woo

Classifications

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D64/665

  the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671) · CPC title

• H10D62/80

  characterised by the materials · CPC title